Abstract: An array substrate of an LCD device includes a glass substrate, an n×m number of pixel electrodes arrayed in a matrix form on the glass substrate, an n-number of scanning lines formed along rows of the pixel electrodes on the glass substrate, an m-number of signal lines formed along columns of the pixel electrodes on the glass substrate, switching elements formed on the glass substrate and located adjacent to intersections of the scanning lines and signal lines, each switching element supplying a video signal from the signal line to the pixel electrode in response to a scanning signal supplied from the scanning line, and a test supporting circuit for sensing potentials of the scanning lines.

Abstract: The display device includes a display panel section and a video signal line driving circuit (281). The display panel section (281) includes a plurality of pixel electrodes arranged in a matrix pattern; a plurality of switching elements each arranged in correspondence to each pixel electrode; a plurality of scanning lines each connected in common to the switching elements corresponding to the pixel electrodes arranged in a same row direction, for transmitting a control signal for opening and closing the common-connected switching elements simultaneously; a plurality of video signal lines for transmitting video signals to the pixel electrodes arranged in a same column direction via the corresponding switching elements, respectively; and an opposing electrode arranged so as to be opposed to the pixel electrodes.

Abstract: A display device comprises a display panel, a scanning circuit section for supplying a scanning signal to scanning lines of the display panel, and a scanning control circuit section for supplying an n-bit (n: 2 or more positive integer) input numeral signal and an inverted replica of the input numeral signal to the scanning circuit section. In the display device, a scanning circuit section comprises an input connection line group having sets of input connection lines for receiving bits of the input numeral signal and bits of the inverted replica of the input numeral signal, a plurality of logic circuit sections, less in number than the scanning lines, for responding to combinations of the input numeral signal and its inverted replica, and an output distributing unit for assigning an output from one logic circuit section to at least two scanning lines.

Abstract: A display device comprises a display panel, a scanning circuit section for supplying a scanning signal to scanning lines of the display panel, and a scanning control circuit section for supplying an n-bit (n: 2 or more positive integer) input numeral signal and an inverted replica of the input numeral signal to the scanning circuit section. In the display device, a scanning circuit section comprises an input connection line group having sets of input connection lines for receiving bits of the input numeral signal and bits of the inverted replica of the input numeral signal, a plurality of logic circuit sections, less in number than the scanning lines, for responding to combinations of the input numeral signal and its inverted replica, and an output distributing unit for assigning an output from one logic circuit section to at least two scanning lines.

Abstract: An array substrate of an LCD device includes a glass substrate, an n.times.m number of pixel electrodes arrayed in a matrix form on the glass substrate, an n-number of scanning lines formed along rows of the pixel electrodes on the glass substrate, an m-number of signal lines formed along columns of the pixel electrodes on the glass substrate, switching elements formed on the glass substrate and located adjacent to intersections of the scanning lines and signal lines, each switching element supplying a video signal from the signal line to the pixel electrode in response to a scanning signal supplied from the scanning line, and a test supporting circuit for sensing potentials of the scanning lines.

Abstract: A liquid crystal display is described which comprises a plurality of switching elements each including an active region disposed between a drain region and a source region, a pair of pixel elements respectively connected to the drain regions of switching elements, a signal line connecting between a signal line driving circuit and the drain region of the switching element and being disposed between the pair of the pixel elements, a storage capacitor line including a portion disposed between the pair of the pixel elements, and a first dielectric layer interposed between the signal line and the storage capacitor line portion.

Abstract: In an oscillator of the invention, the shape and position of each chip and wiring between the chips are optimally designed. Since a SAW element and an IC which have satisfactory reliability are arranged in the same package, the oscillator is not greatly influenced by external electromagnetic induction, is not unstably oscillated, and has satisfactory reliability.

Abstract: A modulator includes a plurality of piezoelectric resonators, a plurality of oscillator circuits, arranged in a one-to-one correspondence with the plurality of piezoelectric resonators, for generating different frequency signals in correspondence with corresponding piezoelectric resonators, and a switching circuit for selecting a predetermined frequency signal from the plurality of different frequency signals on the basis of a value of a digital signal to be modulated, and for outputting the selected frequency signal as a modulation signal.

Abstract: In an oscillator of this invention, a differential amplifier circuit is constituted by connecting the collectors of first and second transistors to one terminal of a DC power source respectively through first and second resistors, the emitters of the first and second transistors to the other terminal of the DC power source through a common current-source, and the bases of the first and second transistors to a bias circuit for applying a bias voltage, at least one port of a piezo-electric device having at least two ports on a single substrate is connected between the collectors of the first and second transistors, and the remaining port is connected between the bases of the first and second transistors. The transistors can be field effect transistors, and the common current-source can be a resistor. In this oscillator, since no DC voltage is applied across transducers of each port, degradation of a piezo-electric device can be prevented.

Abstract: A resonance inverter includes a DC power source, a resonance capacitor, an inductor, and a plurality of semiconductor switches. The resonance capacitor and inductor form a parallel resonant circuit. The inverter further includes control means for detecting a peak value of the voltage across the resonance capacitor, and for alternately conducting said semiconductor switches with a certain lead phase with respect to the peak point of the capacitor terminal voltage.

Abstract: A switching power supply has a saturable transformer provided with first to fourth windings. The first winding is inserted in series in a first path from a DC power source to a primary winding of a power transmitting transformer. A main switch is inserted in series in the first path and controlled by an output of the second winding. The operation of the main switch is positively fed back through the saturable transformer. A capacitor is connected in parallel to a series circuit consisting of the main switch and the first winding. An auxiliary source for generating a predetermined direct current output is provided to drive the third winding by a polarity opposite to that of the first winding. An auxiliary switch is inserted in series in a second path from the auxiliary source to the third winding and controlled by an output of the fourth winding. The operation of the auxiliary switch is positively fed back through the saturable transformer.

Abstract: A single ended, separately driven, resonant DC-DC converter including a transformer, a capacitor connected in parallel with a primary winding of the transformer, a switching transistor connected between one end of the primary winding of the transformer and one end of a DC power source, and a blocking oscillating circuit for driving the switching transistor. The blocking oscillating circuit is directly driven by the DC power source and contains circuits for properly setting a pulse width and a pulse stop period of output pulses from the blocking oscillating circuit.

Abstract: A single-ended switching circuit is constituted by a primary winding of a transformer, a switching circuit connected between the primary winding and a DC power supply and on-off operated with a predetermined cycle and also with a predetermined "on" period and a resonance capacitor connected in parallel with the primary winding. A magnetic amplifier, a rectifying element and a choke coil are connected in series between a secondary side circuit of the transformer and the load. The magnetic amplifier includes a saturable reactor which is held saturated during a half cycle of the voltage induced in a secondary winding of the transformer and remains unsaturated during the other half cycle of the voltage.

Abstract: A switching element is connected between a power supply and the primary winding of a transformer, and it is on-off controlled with a predetermined cycle and with a predetermined conducting period. The secondary winding of the transformer is connected to a parallel circuit of a filtering capacitor and a load via a rectifier diode and a choke coil. A closed circuit, to which the reflux current of the choke coil flows through the parallel circuit of the filtering capacitor and load, is formed by a reflux diode.

Abstract: A series circuit of a transistor serving as a switching element and an input power supply is connected in parallel with the primary side inductor of a transformer. A resonance capacitor and a damping diode are connected in parallel with the transistor. When the transistor is turned on in response to a pulse signal supplied from a pulse generator, the current from a DC power supply is supplied to the transformer. At the same time, a commutating diode is turned on to supply the output current from the transformer to a load resistor.

Abstract: A high frequency switching circuit in which, to reduce power dissipation of a switching element, the characteristic impedance defined by the inductance of a transformer connected in series with the switching element and the capacitance of a capacitor connected in parallel with the switching element, the ratio of the input voltage and an output voltage, and the ratio of ON time and a switching period T of the switching element are each selected within a given range. Alternatively, a ratio pertaining to a leakage inductance of the transformer and an inductance of an additional inductor, and a ratio pertaining to the output and input voltages are selected to satisfy a predetermined relation and the characteristic impedance is selected within a given range.