Abstract: A high-voltage MOS transistor has a semiconductor substrate formed with a first well of a first conductivity type in which a drain region and a drift region are formed and a second well of a second, opposite conductivity type in which a source region and a channel region are formed, a gate electrode extends over the substrate from the second well to the first well via a gate insulation film, wherein there is formed a buried insulation film in the drift region underneath the gate insulation film at a drain edge of the gate electrode, there being formed an offset region in the semiconductor substrate between the channel region and the buried insulation film, wherein the resistance of the offset region is reduced in a surface part thereof by being introduced with an impurity element of the first conductivity type with a concentration exceeding the first well.

Abstract: A semiconductor device includes two Dt-MOS transistors each having insulation regions respectively under the source and drain regions, the two Dt-MOS transistors sharing a diffusion region as a source region of one Dt-MOS transistor and a drain region of the other Dt-MOS transistor, wherein the insulation regions have respective bottom edges located lower than bottom edges of respective body regions of the Dt-MOS transistors, and wherein the bottom edges of the respective body regions are located deeper than respective bottom edges of the source and drain regions of the Dt-MOS transistors.

Abstract: A method of manufacturing a semiconductor device, in which an amorphous silicon layer is formed into a shape of a gate electrode of a MOS transistor, and then impurity is implanted to a surface of a silicon substrate from a diagonal direction using the amorphous silicon layer as a mask.

Abstract: A high-voltage MOS transistor has a semiconductor substrate formed with a first well of a first conductivity type in which a drain region and a drift region are formed and a second well of a second, opposite conductivity type in which a source region and a channel region are formed, a gate electrode extends over the substrate from the second well to the first well via a gate insulation film, wherein there is formed a buried insulation film in the drift region underneath the gate insulation film at a drain edge of the gate electrode, there being formed an offset region in the semiconductor substrate between the channel region and the buried insulation film, wherein the resistance of the offset region is reduced in a surface part thereof by being introduced with an impurity element of the first conductivity type with a concentration exceeding the first well.

Abstract: A semiconductor device includes two Dt-MOS transistors each having insulation regions respectively under the source and drain regions, the two Dt-MOS transistors sharing a diffusion region as a source region of one Dt-MOS transistor and a drain region of the other Dt-MOS transistor, wherein the insulation regions have respective bottom edges located lower than bottom edges of respective body regions of the Dt-MOS transistors, and wherein the bottom edges of the respective body regions are located deeper than respective bottom edges of the source and drain regions of the Dt-MOS transistors.

Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode, a source region and a drain region, forming a first metal layer, forming silicide layers by first annealing, removing a remainder of the first metal layer after the first annealing, performing a second annealing, forming a second metal layer, performing a third annealing, and removing a remainder of the second metal layer.

Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode, a source region and a drain region, forming a first metal layer, forming silicide layers by first annealing, removing a remainder of the first metal layer after the first annealing, performing a second annealing, forming a second metal layer, performing a third annealing, and removing a remainder of the second metal layer.

Abstract: An impurity-diffused layer having an extension structure is formed first by implanting Sb ion as an impurity for forming a pocket region; then by implanting N as a diffusion-suppressive substance so as to produce two peaks in the vicinity of the interface with a gate electrode and at an amorphous/crystal interface which serves as an defect interface generated by the impurity in the pocket region; and by carrying out ion implantations for forming an extension region and deep source and drain regions.

Abstract: A method of manufacturing a semiconductor device, in which an amorphous silicon layer is formed into a shape of a gate electrode of a MOS transistor, and then impurity is implanted to a surface of a silicon substrate from a diagonal direction using the amorphous silicon layer as a mask.

Abstract: In consideration of an optimum combination of impurities used for the purpose of forming an extension region (13) and a pocket region (11) and further inhibiting impurity diffusion in the extension region (13) when an impurity diffusion layer (21) is formed in a semiconductor device having an nMOS structure, at least phosphorus (P) is used as an impurity in the extension region (13), at least indium (In) is used as an impurity in the pocket region (11), and additionally carbon (C) is used as a diffusion inhibiting substance. Consequently, it is possible to easily and surely realize the scaling down/high integration of elements while improving threshold voltage roll-off characteristics and current drive capability and reducing a drain leakage current especially in the semiconductor device having the nMOS structure, and particularly by making the optimum design of a semiconductor device having a CMOS structure possible, improve device performance and reduce power consumption.

Abstract: A method of manufacturing a semiconductor device, in which an amorphous silicon layer is formed into a shape of a gate electrode of a MOS transistor, and then impurity is implanted to a surface of a silicon substrate from a diagonal direction using the amorphous silicon layer as a mask.

Abstract: In consideration of an optimum combination of impurities used for the purpose of forming an extension region (13) and a pocket region (11) and further inhibiting impurity diffusion in the extension region (13) when an impurity diffusion layer (21) is formed in a semiconductor device having an nMOS structure, at least phosphorus (P) is used as an impurity in the extension region (13), at least indium (In) is used as an impurity in the pocket region (11), and additionally carbon (C) is used as a diffusion inhibiting substance. Consequently, it is possible to easily and surely realize the scaling down/high integration of elements while improving threshold voltage roll-off characteristics and current drive capability and reducing a drain leakage current especially in the semiconductor device having the nMOS structure, and particularly by making the optimum design of a semiconductor device having a CMOS structure possible, improve device performance and reduce power consumption.

Abstract: In consideration of an optimum combination of impurities used for the purpose of forming an extension region (13) and a pocket region (11) and further inhibiting impurity diffusion in the extension region (13) when an impurity diffusion layer (21) is formed in a semiconductor device having an nMOS structure, at least phosphorus (P) is used as an impurity in the extension region (13), at least indium (In) is used as an impurity in the pocket region (11), and additionally carbon (C) is used as a diffusion inhibiting substance. Consequently, it is possible to easily and surely realize the scaling down/high integration of elements while improving threshold voltage roll-off characteristics and current drive capability and reducing a drain leakage current especially in the semiconductor device having the nMOS structure, and particularly by making the optimum design of a semiconductor device having a CMOS structure possible, improve device performance and reduce power consumption.

Abstract: A semiconductor device that can operate at plural kinds of power supply voltages. A pocket region which is adjacent to a source region and the conduction type of which is the same as that of a channel region formed between the source region and a drain region is formed. By doing so, an asymmetrical profile of impurity concentration in which impurity concentration on a source-region side of a region between the source region and the drain region is high and in which impurity concentration on a drain-region side of the region between the source region and the drain region is low is obtained. As a result, an electric current generated by impact ionization at the time of a drain bias being applied decreases. Therefore, a deterioration in the characteristics of the semiconductor device caused by hot carriers can be reduced. That is to say, the semiconductor device's resistance to hot carriers improves, so the semiconductor device can operate at the plural kinds of power supply voltages.

Abstract: An impurity-diffused layer having an extension structure is formed first by implanting Sb ion as an impurity for forming a pocket region; then by implanting N as a diffusion-suppressive substance so as to produce two peaks in the vicinity of the interface with a gate electrode and at an amorphous/crystal interface which serves as an defect interface generated by the impurity in the pocket region; and by carrying out ion implantations for forming an extension region and deep source and drain regions.

Abstract: An impurity-diffused layer having an extension structure is formed first by implanting Sb ion as an impurity for forming a pocket region; then by implanting N as a diffusion-suppressive substance so as to produce two peaks in the vicinity of the interface with a gate electrode and at an amorphous/crystal interface which serves as an defect interface generated by the impurity in the pocket region; and by carrying out ion implantations for forming an extension region and deep source and drain regions.

Abstract: In consideration of an optimum combination of impurities used for the purpose of forming an extension region (13) and a pocket region (11) and further inhibiting impurity diffusion in the extension region (13) when an impurity diffusion layer (21) is formed in a semiconductor device having an nMOS structure, at least phosphorus (P) is used as an impurity in the extension region (13), at least indium (In) is used as an impurity in the pocket region (11), and additionally carbon (C) is used as a diffusion inhibiting substance. Consequently, it is possible to easily and surely realize the scaling down/high integration of elements while improving threshold voltage roll-off characteristics and current drive capability and reducing a drain leakage current especially in the semiconductor device having the nMOS structure, and particularly by making the optimum design of a semiconductor device having a CMOS structure possible, improve device performance and reduce power consumption.

Abstract: An impurity-diffused layer having an extension structure is formed first by implanting Sb ion as an impurity for forming a pocket region; then by implanting N as a diffusion-suppressive substance so as to produce two peaks in the vicinity of the interface with a gate electrode and at an amorphous/crystal interface which serves as an defect interface generated by the impurity in the pocket region; and by carrying out ion implantations for forming an extension region and deep source and drain regions.