Abstract: Color correction is performed on a first set of three pixel values by determining a color phase of the pixel values. The determined color phase is used to determine a phase difference, and the phase difference is used to control an amount of color phase rotation applied to the chrominance pixel values of the first set. The color phase is also used to determine a first gain, and the first gain is used to control a scaling of the rotated chrominance pixel values, thereby generating color corrected chrominance pixel values. The color phase is also used to determine a second gain, and the second gain is used to control an amount of scaling applied to the luminance pixel value of the first set, thereby generating the color corrected luminance pixel value. How color phase determines phase difference, the first gain and the second gain is changed depending on lighting conditions.

Abstract: Color correction is performed on a first set of three pixel values by determining a color phase of the pixel values. The determined color phase is used to determine a phase difference, and the phase difference is used to control an amount of color phase rotation applied to the chrominance pixel values of the first set. The color phase is also used to determine a first gain, and the first gain is used to control a scaling of the rotated chrominance pixel values, thereby generating color corrected chrominance pixel values. The color phase is also used to determine a second gain, and the second gain is used to control an amount of scaling applied to the luminance pixel value of the first set, thereby generating the color corrected luminance pixel value. How color phase determines phase difference, the first gain and the second gain is changed depending on lighting conditions.

Abstract: A nonvolatile semiconductor memory includes a memory unit, memory control unit, defect position detection unit, and data correction unit. The memory unit has a plurality of memory cells to discretely store an analog signal such as an image signal as analog data in the form of an analog value. The memory control unit sequentially selects the memory cells as a read out target of the memory unit in response to a predetermined clock. The defect position detection unit detects, on the basis of defect position information indicating a position of defective analog data included in the analog data read out from the memory unit, whether a memory cell corresponding to the defect position is selected by the memory control unit, and outputs a detection output. The data correction unit corrects the analog data at the defect position in accordance with the detection output from the defect position detection unit by using another analog data of the analog signal stored in said memory unit.

Abstract: A signal conversion processing apparatus for temporarily storing an input analog signal and processing the signal to generate a desired output signal includes nonvolatile semiconductor memory sections, an input control section, and a signal processing section. The nonvolatile semiconductor memory sections sequentially store the input analog signal on the basis of a predetermined first control signal in the form of an analog value. The input control section selects a nonvolatile semiconductor memory section, in which the analog signal is to be written, from the nonvolatile semiconductor memory sections on the basis of a predetermined second control signal. The signal processing section performs arithmetic processing of a plurality of analog data read out from the nonvolatile semiconductor memory sections to convert the analog data into a desired output signal in the form of an analog value.

Abstract: A semiconductor memory device includes a memory cell and first and second electrodes. The memory cell has a floating gate formed on a semiconductor substrate via a gate insulating film to be insulated from a remaining part, and a control gate formed on the floating gate via an isolation insulating film. The first electrode is formed on the floating gate via a first insulating film in a region of the floating gate except for a channel region for constituting the memory cell. The second electrode is formed on the floating gate via a second insulating film in a region of the floating gate except for the channel region for constituting the memory cell. When a predetermined voltage is applied to the first and second electrodes, a tunnel current flows through the first and second insulating films.