Abstract: When data erasure of a flash memory is interrupted and restarted from the interrupted point, time required for the data erasure is shortened. A flash memory includes a memory cell(s), a verification circuit, and a power supply circuit. The verification circuit measures a threshold voltage of the memory cell(s) by verifying an erasure state of the memory cell(s). The power supply circuit applies, to the memory cell(s), one or more pulse voltages whose initial pulse voltage has a strength that corresponds to the measured threshold voltage.

Abstract: A memory control circuit includes a conversion circuit performing a conversion processing for parallel readout bit data formed from individual bits read out from memory cells of a nonvolatile memory, by setting the individual bit that is once again read out from the memory cell, which is previously determined to be successfully storing an expectation value, to a corresponding expectation value expected to be stored in the memory cell, and a determination circuit determining a result of a write processing to write parallel expectation value data to the nonvolatile memory, based on the parallel readout bit data converted by the conversion circuit and the parallel expectation value data.

Abstract: A flash memory includes a data area in which first and second k-bit data (k is a natural number) are stored; and an additional data area in which a first additional m-bit data (m is a natural number) and a second additional m-bit data used to respectively identify the first and second data are stored. The first additional data and the second additional data have different values.

Abstract: When data erasure of a flash memory is interrupted and restarted from the interrupted point, time required for the data erasure is shortened. A flash memory includes a memory cell(s), a verification circuit, and a power supply circuit. The verification circuit measures a threshold voltage of the memory cell(s) by verifying an erasure state of the memory cell(s). The power supply circuit applies, to the memory cell(s), one or more pulse voltages whose initial pulse voltage has a strength that corresponds to the measured threshold voltage.

Abstract: A data processing apparatus includes a memory, an additional bit generating unit which generates an additional bit to be added to write expectation values, on a basis of the write expectation values to be written respectively to designated addresses in the memory, the additional bit and the write expectation values being supplied to the memory as write data and stored respectively in memory cells at the addresses, and a write state judging unit which reads stored data retained in the memory cells at the addresses and judges a write state of the memory cells.

Abstract: A memory control circuit according to an embodiment of the present invention includes: a writable/readable memory; a comparison unit comparing write data to write in the memory with read data that is read from a memory address where the write data is written; a comparison result storage unit storing a comparison result compared by the comparison unit in association with the memory address; and a control unit controlling retry processing of rewriting the write data to the memory address determined to be unverified based on the stored comparison result.

Abstract: A memory control circuit includes a conversion circuit performing a conversion processing for parallel readout bit data formed from individual bits read out from memory cells of a nonvolatile memory, by setting the individual bit that is once again read out from the memory cell, which is previously determined to be successfully storing an expectation value, to a corresponding expectation value expected to be stored in the memory cell, and a determination circuit determining a result of a write processing to write parallel expectation value data to the nonvolatile memory, based on the parallel readout bit data converted by the conversion circuit and the parallel expectation value data.

Abstract: A memory control circuit according to an embodiment of the present invention includes: a writable/readable memory; a comparison unit comparing write data to write in the memory with read data that is read from a memory address where the write data is written; a comparison result storage unit storing a comparison result compared by the comparison unit in association with the memory address; and a control unit controlling retry processing of rewriting the write data to the memory address determined to be unverified based on the stored comparison result.

Abstract: A flash memory includes a data area in which first and second k-bit data (k is a natural number) are stored; and an additional data area in which a first additional m-bit data (m is a natural number) and a second additional m-bit data used to respectively identify the first and second data are stored. The first additional data and the second additional data have different values.

Abstract: A testing circuit includes m block test units and a first logical processing unit. The block test unit compares a first data outputted from a test object with a reference data, and outputs a result as a test circuit output signal based on a output control signal. The first logical processing unit judges whether the all of the m test circuit output signals indicate that the first data is coincident with the reference data, and outputs a result as a total judgment result signal based on the m test circuit output signals. The block test unit includes a block judging unit and a block output selecting unit. The block judging unit compares the first data with the reference data to judge whether the first data is coincident with the reference data, and outputs a result as a block judgment result signal.

Abstract: A testing circuit includes m block test units and a first logical processing unit. The block test unit compares a first data outputted from a test object with a reference data, and outputs a result as a test circuit output signal based on a output control signal. The first logical processing unit judges whether the all of m the test circuit output signals indicate that the first data is coincident with the reference data, and outputs a result as a total judgment result signal based on the m test circuit output signals. The block test unit includes a block judging unit and a block output selecting unit. The block judging unit compares the first data with the reference data to judge whether the first data is coincident with the reference data, and outputs a result as a block judgment result signal. The block output selecting unit outputs one of the block judgment result signal and a predetermined standard signal as the test circuit output signal based on the output control signal.

Abstract: A devices is disclosed having at least an internal circuit for performing a predetermined processing and a clock generation circuit for such as an oscillation circuit for providing a clock signal to the internal circuit and other circuits is disclosed. The device has a clock output circuit for receiving a test mode signal and outputting the clock signal or an output from the internal circuit to an output terminal in accordance with the test mode signal. When the test mode signal become active, the clock signal is outputted from the external terminal to perform the test for the clock signal.

Abstract: A semiconductor integrated circuit incorporating therein a clock supply circuit drives a plurality of peripheral circuits using different frequency-divided clocks. In order to avoid enlargement of switching current there is provided a frequency-dividing circuit for dividing external clock supplied from a clock supply terminal, and a plurality of peripheral circuits which are operated by frequency-divided clocks. There is provided a first clock supply circuit which is capable of generating frequency-divided clock with the highest frequency among frequency-divided clocks required by the peripheral circuits, and a plurality of second clock supply circuits for generating frequency-divided clocks from frequency-divided clock of the first clock supply circuit. Wiring to connect the first clock supply circuit to second clock supply circuits becomes short, and the number of wiring is reduced. Therefore it becomes possible to reduce the switching current.

Abstract: A data reading testing method of a microcomputer loaded with a PROM being conducted under a normal operation mode. Setting the operation mode of the microcomputer to a ROM-less mode. Setting the externally extended function under the ROM-less mode. Diverging addresses to an externally extended region. Setting the microcomputer to the normal operation mode, upon which a CPU is to fetch instructions being previously provided to applicable addresses of the externally extended region, and to read the data from the PROM. Reading the data from the PROM. Evaluating the read data and terminating the reading test.

Abstract: In a semiconductor device formed on a semiconductor wafer, writing unit writes a result signal into an unvolatile memory. A testing unit tests whether or not an execution unit of the semiconductor device executes a predetermined function correctly and produces the result signal. The result signal is used to diagnose the semiconductor devise itself. The execution unit may be included in the unvolatile memory.