Patents by Inventor YOU-JIN JUNG

YOU-JIN JUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240424134
    Abstract: The present disclosure relates to a novel hydrophobic peptide consisting of short amino acid sequences as repeat units, having a perfectly stabilized ?-helix structure without help from outside. The peptide has no cytotoxicity and has magnetic responsiveness, i.e., its arrangement and orientation are controlled by a magnetic field. In addition, the hydrophobic peptide according to the present disclosure can not only form complexes of various structures with hydrophilic molecules but also provide suitable nanostructures such as nanoribbons and artificial chromosome-like structures through stepwise association with nucleic acid materials.
    Type: Application
    Filed: November 22, 2023
    Publication date: December 26, 2024
    Applicant: UIF (University Industry Foundation), Yonsei University
    Inventors: Yong-beom LIM, You-Jin JUNG, Hyoseok KIM
  • Patent number: 10910279
    Abstract: A variable resistance memory device includes a memory unit including a first electrode, a variable resistance pattern and a second electrode sequentially stacked on a substrate, a first selection structure on the memory unit, a third electrode structure on the first selection structure, and an anti-fuse including a fourth electrode, a second selection structure and a fifth electrode structure sequentially stacked. The fourth electrode directly contacts the second selection structure, and a bottom of the fourth electrode is lower than a bottom of the second electrode.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: February 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: You-Jin Jung, Masayuki Terai
  • Patent number: 10825862
    Abstract: A variable resistance memory device includes: a substrate including a peripheral region and a core region, the core region including a far region spaced apart from the peripheral region and a near region between the far region and the peripheral region; first conductive lines disposed on the substrate and extending in a first direction; second conductive lines disposed on the first conductive lines and extending in a second direction intersecting the first direction, and memory cells disposed between the first and second conductive lines on the core region. The memory cells include a near memory cell disposed on the near region, and a far memory cell disposed on the far region, wherein a resistance or threshold voltage of the near memory cell, controlling connection of each of the memory cells to a corresponding one of the second conductive lines, is different from that of the far memory cell.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghyun Cho, You-Jin Jung, Masayuki Terai, Jinchan Yun
  • Publication number: 20200243764
    Abstract: A variable resistance memory device includes a memory unit including a first electrode, a variable resistance pattern and a second electrode sequentially stacked on a substrate, a first selection structure on the memory unit, a third electrode structure on the first selection structure, and an anti-fuse including a fourth electrode, a second selection structure and a fifth electrode structure sequentially stacked. The fourth electrode directly contacts the second selection structure, and a bottom of the fourth electrode is lower than a bottom of the second electrode.
    Type: Application
    Filed: September 4, 2019
    Publication date: July 30, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: You-Jin JUNG, Masayuki Terai
  • Publication number: 20200111835
    Abstract: A variable resistance memory device includes: a substrate including a peripheral region and a core region, the core region including a far region spaced apart from the peripheral region and a near region between the far region and the peripheral region; first conductive lines disposed on the substrate and extending in a first direction; second conductive lines disposed on the first conductive lines and extending in a second direction intersecting the first direction, and memory cells disposed between the first and second conductive lines on the core region. The memory cells include a near memory cell disposed on the near region, and a far memory cell disposed on the far region, wherein a resistance or threshold voltage of the near memory cell, controlling connection of each of the memory cells to a corresponding one of the second conductive lines, is different from that of the far memory cell.
    Type: Application
    Filed: April 25, 2019
    Publication date: April 9, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: JUNGHYUN CHO, YOU-JIN JUNG, MASAYUKI TERAI, JINCHAN YUN