Abstract: This application provides a video splitting method and an electronic device. When the method is performed by a server, the server processes a long video into a plurality of short videos, and then a terminal obtains the short video from the server and plays the short video; or when the method is performed by a terminal, the terminal obtains a long video from a server, and then the long video is processed into a plurality of short videos, and the plurality of short videos are played.

Abstract: This application provides a video splitting method and an electronic device. When the method is performed by a server, the server processes a long video into a plurality of short videos, and then a terminal obtains the short video from the server and plays the short video; or when the method is performed by a terminal, the terminal obtains a long video from a server, then processes the long video into a plurality of short videos, and plays the plurality of short videos.

Abstract: This application provides a video splitting method and an electronic device. When the method is performed by a server, the server processes a long video into a plurality of short videos, and then a terminal obtains the short video from the server and plays the short video; or when the method is performed by a terminal, the terminal obtains a long video from a server, then processes the long video into a plurality of short videos, and plays the plurality of short videos.

Abstract: A test data integration system and a method thereof are provided. The method includes: collecting, by each of a plurality of client devices, a plurality of test information obtained from coupled automatic test equipment when performing a test operation, and transmitting the plurality of test information to a server; receiving, by the server, the plurality of test information, and generating a graphical user interface according to the plurality of test information and displaying an integration analysis result corresponding to the plurality of test information.

Abstract: A test data integration system and a method thereof are provided. The method includes: collecting, by each of a plurality of client devices, a plurality of test information obtained from coupled automatic test equipment when performing a test operation, and transmitting the plurality of test information to a server; receiving, by the server, the plurality of test information, and generating a graphical user interface according to the plurality of test information and displaying an integration analysis result corresponding to the plurality of test information.

Abstract: A method and a device for processing geological information is disclosed. The method for processing the geological information includes acquiring multiple geological image graphs, determining the relation between the image coordinate and the ground coordinate of each of the multiple geological image graphs by an imaging mode of geological images, and joining the multiple geological image graphs together according to the relation between the image coordinate and the ground coordinate of each of the multiple geological image graphs. Accordingly, large-scale ground images can be acquired by processing the geological images.

Abstract: Disclosed in the disclosure are a method and a device for processing geological information. The method for processing the geological information comprises: acquiring multiple geological image graphs; determining the relation between the image coordinate and the ground coordinate of each of the multiple geological image graphs by an imaging mode of geological images; and joining the multiple geological image graphs together according to the relation between the image coordinate and the ground coordinate of each of the multiple geological image graphs. The large-scale ground images can be acquired by processing the geological images according to the present disclosure.

Abstract: The invention discloses a packaging structure and packaging method. The packaging structure includes a solder bump, a pad located on a front side of a chip, and an intermediate metal layer which connects the solder bump and the pad, wherein a through hole passing from a back side of the chip to the pad is provided on the chip, and the intermediate metal layer is connected to the pad within the through hole. In the packaging structure, a through hole is formed on the back side of the chip to expose the pad on the front side of the chip and the intermediate metal layer is connected to the pad within the through hole. This provides a relatively large contacting area therebetween. The connection thus formed is more reliable and stable, compared with the prior art structure.

Abstract: The present invention relates to an optical converter and a manufacturing method thereof and a light emitting diode. An optical converter for a light emitting diode includes two substrates, in which, a annular first cavity wall is arranged between the two substrates, and an airtight space filled with an optical conversion substance is surrounded by the first cavity wall and the two substrates. The invention implements the encapsulation and manufacturing of the optical conversion substance for the LED. The structure and the manufacturing method according to the invention can be utilized to encapsulate an active optical conversion substance in the optical converter while avoiding the active optical conversion substance reacting to other active substance, e.g., oxygen, during manufacturing. Furthermore, the optical conversion substance is encapsulated with wafer level chip size packaging to thereby improve the efficiency of manufacturing the optical converter and reduce the cost.

Abstract: The invention discloses a packaging structure and packaging method. The packaging structure includes a solder bump, a pad located on a front side of a chip, and an intermediate metal layer which connects the solder bump and the pad, wherein a through hole passing from a back side of the chip to the pad is provided on the chip, and the intermediate metal layer is connected to the pad within the through hole. In the packaging structure, a through hole is formed on the back side of the chip to expose the pad on the front side of the chip and the intermediate metal layer is connected to the pad within the through hole. This provides a relatively large contacting area therebetween. The connection thus formed is more reliable and stable, compared with the prior art structure.

Abstract: The present invention disclosed a wafer level chip size packaged chip device with a double-layer lead structure and methods of fabricating the same. The double-layer lead is designed to meet a tendency of increasing quantity per area of peripheral arrayed compatible pads on a semiconductor chip, and also to save more space for layout of lead on the chip bottom surface for avoiding potential short inbetween which happen in increasing probability with increasing quantity per area on the condition of one-layer lead.

Abstract: The present invention provide a wafer level chip size packaged chip device with a N-shape junction at which external leads electrically connect to peripheral arrayed compatible pads and a method of fabricating the same. In the wafer level chip size package, with such an n-shape junction instead of a conventional T-shape junction observed in Shellcase type wafer level chip size package technology, electrical connections between compatible pads and external leads are more reliable due to larger connection area than the counterpart in the T-shape junction.

Abstract: The present invention disclosed a wafer level chip size packaged chip device with a double-layer lead structure and methods of fabricating the same. The double-layer lead is designed to meet a tendency of increasing quantity per area of peripheral arrayed compatible pads on a semiconductor chip, and also to save more space for layout of lead on the chip bottom surface for avoiding potential short inbetween which happen in increasing probability with increasing quantity per area on the condition of one-layer lead.

Abstract: The present invention provide a wafer level chip size packaged chip device with a N-shape junction at which external leads electrically connect to peripheral arrayed compatible pads and a method of fabricating the same. In the wafer level chip size package, with such an n-shape junction instead of a conventional T-shape junction observed in Shellcase type wafer level chip size package technology, electrical connections between compatible pads and external leads are more reliable due to larger connection area than the counterpart in the T-shape junction.