Patents by Inventor Youming Liu

Youming Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230335430
    Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base; forming a plurality of first trenches arranged in parallel at intervals and extending along a first direction, and an initial active region between two adjacent ones of the first trenches, wherein the initial active region includes a first initial source-drain region close to a bottom of the first trench, a second initial source-drain region away from the bottom of the first trench, and an initial channel region located between the first initial source-drain region and the second initial source-drain region; forming a protective dielectric layer, wherein the protective dielectric layer covers a sidewall of the second initial source-drain region and a sidewall of the initial channel region; thinning the first initial source-drain region.
    Type: Application
    Filed: June 27, 2022
    Publication date: October 19, 2023
    Inventors: Guangsu Shao, Deyuan Xiao, Yunsong Qiu, Youming Liu, Yi Jiang, Xingsong Su, Yuhan Zhu
  • Publication number: 20230301064
    Abstract: The present disclosure relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a forming method thereof. The forming method of a semiconductor device includes: providing a substrate; etching the substrate to form first recesses and second recesses located below the first recesses and communicating with the first recesses; forming a bit line in the second recesses; forming, at bottoms of the first recesses, an isolation layer covering the bit line; enlarging an inner diameter of the first recess above the isolation layer; and forming a gate layer on a sidewall of the first recess whose inner diameter is enlarged.
    Type: Application
    Filed: June 8, 2022
    Publication date: September 21, 2023
    Inventors: Guangsu SHAO, Deyuan XIAO, Yunsong QIU, Youming LIU
  • Publication number: 20230018716
    Abstract: A semiconductor structure includes a plurality memory group provided in rows, each of the memory groups includes a plurality of memories arranged at intervals along a row direction, and for two adjacent ones of the memory groups, the memories in one memory group and the memories in another memory group are staggered.
    Type: Application
    Filed: September 23, 2022
    Publication date: January 19, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: YI JIANG, Deyuan XIAO, Xingsong SU, YOUMING LIU
  • Publication number: 20230020883
    Abstract: A semiconductor structure includes a substrate and a plurality of word lines located on a top surface of the substrate. Each of the word lines extends in a direction perpendicular to the top surface of the substrate. The plurality of word lines are arranged at intervals along a first direction. Any two adjacent ones of the word lines are arranged in an at least partially staggered manner along the first direction. The first direction is a direction parallel to the top surface of the substrate.
    Type: Application
    Filed: September 21, 2022
    Publication date: January 19, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: YOUMING LIU, Deyuan XIAO
  • Publication number: 20230010014
    Abstract: A method for manufacturing a semiconductor structure includes the following operations. A substrate is provided, and is etched to form first isolation trenches in a cell region and a second isolation trench in a peripheral region. A first isolation dielectric layer is filled in each of the first isolation trenches and an isolation structure is formed in the second isolation trench. A patterned mask layer is formed on surfaces of the cell region and the peripheral region. The substrate and the first isolation dielectric layer are etched based on the patterned mask layer to form the third isolation trenches extending along a second direction. The third and first isolation trenches isolate multiple active pillars. The active pillar includes a first connecting end, a second connecting end and a channel region.
    Type: Application
    Filed: September 22, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Guangsu SHAO, Deyuan XIAO, YOUMING LIU, Yunsong QIU
  • Publication number: 20220393020
    Abstract: Embodiments provide a method for fabricating a semiconductor structure. The method includes: providing a substrate, where the substrate includes semiconductor channels arranged in an array along a first direction and a second direction, and a part of the substrate is exposed between adjacent semiconductor channels; forming a spacer positioned between adjacent semiconductor channels, where a top surface of the spacer is lower than top surfaces of the semiconductor channels; forming a bit line positioned in the substrate, where a top surface of the bit line contacts and connects bottom surfaces of the semiconductor channels; forming a protective layer, where a part of the protective layer is positioned on the top surface of the spacer between the semiconductor channels arranged along the second direction, and another part of the protective layer is positioned on the top surface of the spacer between the semiconductor channels arranged along the first direction.
    Type: Application
    Filed: August 18, 2022
    Publication date: December 8, 2022
    Inventors: Youming LIU, Deyuan XIAO
  • Publication number: 20220392901
    Abstract: Embodiments provide a semiconductor structure. The semiconductor structure includes a substrate, a dielectric layer arranged on the substrate, and a plurality of memory cell layers. The plurality of memory cell layers are spaced in the dielectric layer along a first direction, and projections of any adjacent two of the plurality of memory cell layers on the substrate are overlapped. Each of the plurality of memory cell layers includes a plurality of memory cells spaced along a second direction. According to the embodiments, the plurality of memory cell layers are spaced in the dielectric layer along a direction perpendicular to the substrate, and each of the plurality of memory cell layers has a plurality of memory cells therein; and a source, a channel and a drain in each of the plurality of memory cells are arranged along a direction parallel to the substrate.
    Type: Application
    Filed: August 15, 2022
    Publication date: December 8, 2022
    Inventors: Youming LIU, Deyuan XIAO, Xingsong SU
  • Patent number: 6468596
    Abstract: A magnetic recording medium is formed with enhanced tribological performance by applying a raw, unfractionated lubricant having a wide molecular weight distribution over a disk surface and treating the deposited lubricant with a laser light beam to effect in-situ fractionation of the lubricant to a very narrow molecular weight distribution. Embodiments of the present invention also include laser treating a deposited lubricant to increase the thickness of the bonded lube layer.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: October 22, 2002
    Assignee: Seagate Technology LLC
    Inventors: Youming Liu, Jialuo Jack Xuan, Xiaohua Shel Yang, Chung-Yuang Shih, Vidya K. Gubbi
  • Patent number: 6416839
    Abstract: Stiction failure of a magnetic recording medium is reduced by forming a lubricant topcoat having a first thickness over the landing zone greater than a second thickness over the data zone, with a sharp transition step having an angle of at least about 70° with respect to a line perpendicular to the surface. Embodiments include depositing a lubricant topcoat at a substantially uniform thickness and reducing the thickness of the lubricant topcoat over the data zone by about 20% to about 80% employing a laser light beam to volatilize the lubricant.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: July 9, 2002
    Assignee: Seagate Technology LLC
    Inventors: Jialuo Jack Xuan, Chung-Yuang Shih, Xiaohua Shel Yang, Youming Liu, Vidya K. Gubbi
  • Patent number: 6221442
    Abstract: Stiction failure of a magnetic recording medium is reduced by forming a lubricant topcoat having a first thickness over the landing zone greater than a second thickness over the data zone, with a sharp transition step having an angle of at least about 70° with respect to a line perpendicular to the surface. Embodiments include depositing a lubricant topcoat at a substantially uniform thickness and reducing the thickness of the lubricant topcoat over the data zone by about 20% to about 80% employing a laser light beam to volatilize the lubricant.
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: April 24, 2001
    Assignee: Seagate Technology LLC
    Inventors: Jialuo Jack Xuan, Chung-Yuang Shih, Xiaohua Shel Yang, Youming Liu, Vidya K. Gubbi