Patents by Inventor Youn-ho HONG

Youn-ho HONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11982705
    Abstract: A substrate analysis apparatus is provided. The substrate analysis includes: an interlayer conveying module configured to transport a first FOUP; an exchange module which is connected to the interlayer conveying module, and configured to transfer a wafer from the first FOUP to a second FOUP; a pre-processing module configured to form a test wafer piece using the wafer inside the second FOUP; an analysis module configured to analyze the test wafer piece; and a transfer rail configured to transport the second FOUP containing the wafer and a tray containing the test wafer piece. The wafer includes a first identifier indicating information corresponding to the wafer, the test wafer piece includes a second identifier indicating information generated by the pre-processing module which corresponds to the test wafer piece, and the analysis module is configured to analyze the first identifier and the second identifier in connection with each other.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: May 14, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youn Gon Oh, Ji Hun Kim, Sae Yun Ko, Gil Ho Gu, Dong Su Kim, Eun Hee Lee, Ho Chan Lee, Seong Sil Jeong, Seong Pyo Hong
  • Publication number: 20240089124
    Abstract: Disclosed herein are an apparatus and method for mutual authentication of quantum entities based on Measurement-Device-Independent Quantum Key Distribution (MDI-QKD). The method may include configuring a quantum input form based on an authentication key shared in advance with a counterpart entity, applying polarization modulation to the configured quantum input form, transmitting the quantum input form to which polarization modulation is applied to a quantum measurement device, and authenticating the counterpart entity by checking whether the counterpart entity configures a quantum input form according to the shared authentication key using a measurement result and information about polarization modulation.
    Type: Application
    Filed: March 24, 2023
    Publication date: March 14, 2024
    Inventors: Chang-Ho HONG, Se-Wan JI, O-Sung KWON, Youn-Chang JEONG, Eun-Ji KIM, Seok KIM, Haeng-Seok KO, Dae-Sung KWON, Jin-Gak JANG
  • Patent number: 10366769
    Abstract: Provided is a programming method of a nonvolatile memory device, the method comprising the steps of a first programming loop including applying a first verifying voltage to word lines of a plurality of first memory cells for being programmed in a first programming state of a first target threshold voltage and detecting, from among the plurality of first memory cells, a first slow memory cell whose threshold voltage is less than the first verifying voltage, a second programming loop including applying a first program pulse to the first memory cells and applying a second program pulse to the first slow memory cell, a voltage level of the second program pulse of the second program loop being greater than a voltage level of the first program pulse of the second program loop, and a third programming loop.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 30, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-sung Cho, Il-han Park, Jung-yun Yun, Youn-ho Hong
  • Publication number: 20180211715
    Abstract: Provided is a programming method of a nonvolatile memory device, the method comprising the steps of a first programming loop including applying a first verifying voltage to word lines of a plurality of first memory cells for being programmed in a first programming state of a first target threshold voltage and detecting, from among the plurality of first memory cells, a first slow memory cell whose threshold voltage is less than the first verifying voltage, a second programming loop including applying a first program pulse to the first memory cells and applying a second program pulse to the first slow memory cell, a voltage level of the second program pulse of the second program loop being greater than a voltage level of the first program pulse of the second program loop, and a third programming loop.
    Type: Application
    Filed: November 13, 2017
    Publication date: July 26, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yong-sung CHO, Il-han PARK, Jung-yun YUN, Youn-ho HONG