Abstract: A hardware architecture and a processing method for an activation function in a neural network are provided. A look-up table, which is a corresponding relation among multiple input ranges and linear functions, is provided. A difference between an initial value and an end value of the input range of each linear function is an exponentiation of base-2. These linear functions form a piecewise linear function to approximate the activation function. At least one bit value of an input value is used as an index to query the look-up table to determine a corresponding linear function. The part of bits value of the input value is fed into the determined linear function to obtain an output value. Accordingly, a range comparison may be omitted, and the number of bits of a multiplier-accumulator may be reduced, so as to achieve the objectives of low costs and low power consumption.

Abstract: A computing system and a compressing method for neural network parameters are provided. In the method, multiple neural network parameters are obtained. The neural network parameters are used for a neural network algorithm. Every at least two neural network parameters are grouped into an encoding combination. The number of neural network parameters in each encoding combination is the same. The encoding combinations are compressed with the same compression target bit number. Each encoding combination is compressed independently. The compression target bit number is not larger than a bit number of each encoding combination. Thereby, the storage space can be saved and excessive power consumption for accessing the parameters can be prevented.

Abstract: A feature map caching method of a convolutional neural network includes a connection analyzing step and a plurality of layer operation steps. The connection analyzing step is for analyzing a network to establish a convolutional neural network connection list. The convolutional neural network connection list includes a plurality of tensors and a plurality of layer operation coefficients. Each of the layer operation coefficients includes a step index, at least one input operand label and an output operand label. The step index as a processing order for the layer operation step. At least one of the layer operation steps is for flushing at least one of the tensors in a cache according to a distance between the at least one of the layer operation steps and a future layer operation step of the layer operation steps. The distance is calculated according to the convolutional neural network connection list.

Abstract: A memory-adaptive processing method for a convolutional neural network includes a feature map counting step, a size relation counting step and a convolution calculating step. The feature map counting step is for counting a plurality of input channels of an input feature map tile and a plurality of output channels of an output feature map tile for a convolutional layer operation of the convolutional neural network. The size relation counting step is for obtaining a cache free space size in a feature reap cache and counting a size relation among a total input size, a total output size and the cache free space size of the feature map cache. The convolution calculating step is for performing the convolutional layer operation according to a memory-adaptive processing technique.

Abstract: A fast vector multiplication and accumulation circuit is applied to an artificial neural network accelerator and configured to calculate an inner product of a multiplier vector and a multiplicand vector. A scheduler is configured to arrange a plurality of multiplicands of the multiplicand vector into a plurality of scheduled operands according to a plurality of multipliers of the multiplier vector, respectively. A self-accumulating adder is signally connected to the scheduler and includes a compressor, at least two delay elements and at least one shifter. The compressor is configured to add the scheduled operands to generate a plurality of compressed operands. The at least two delay elements are connected to the compressor. The shifter is configured to shift one of the compressed operands. An adder is signally connected to the output ports of the compressor so as to add the compressed operands to generate the inner product.

Abstract: An apparatus of automatic vehicle suspension system is provided. Road conditions are precisely monitored for reducing vibrations of cabin. Uneven road surface is crossed over through fast expansion and compression of shock absorber just in time. The present invention uses real-time control of an active suspension system to build road contour at real time. At the same time, control signals having better suspension dynamic characteristics are updated at real time for further obtaining a superior and precise suspension system.

Abstract: The present invention discloses a power booting sequence control system and the control method thereof, which optimizes a power booting sequence of a plurality of power switches in an integrated circuit. An initial module initializes a target charge value, a preset current budget and a plurality of time intervals. A current lookup module obtains a booting current across a power switch from a built-in current lookup table. A first computing unit and a second computing unit compute a first and a second power switch numbers respectively. A processing module selects the small number of the first and the second power switch number to get a maximum number of power booting switches under the time intervals, and opens the maximum number of the power booting switches. Therefore, the system keeps the in-rush current value under the preset current budget and speeds up the ramp-up time in a power booting state.

Abstract: A compression method and a compression system for display frames of QFHD (quad full high definition) resolution are provided and applied to the image encoding/decoding environment of the H.264/AVC image encoding standard of the QFHD resolution and the effective dictionary base compression and de-compression algorithm, the image data compression rate can be tremendously raised at the resolution of 1080 HD (High Definition) content and the average memory data rate is greatly decreased. Hence only a bus with a lower frequency as 57 MHz can be done for the real-time of the resolution of 1080 HD content.

Abstract: The present invention discloses a power booting sequence control system and the control method thereof, which optimizes a power booting sequence of a plurality of power switches in an integrated circuit. An initial module initializes a target charge value, a preset current budget and a plurality of time intervals. A current lookup module obtains a booting current across a power switch from a built-in current lookup table. A first computing unit and a second computing unit compute a first and a second power switch numbers respectively. A processing module selects the small number of the first and the second power switch number to get a maximum number of power booting switches under the time intervals, and opens the maximum number of the power booting switches. Therefore, the system keeps the in-rush current value under the preset current budget and speeds up the ramp-up time in a power booting state.

Abstract: A compression method and a compression system for display frames of QFHD (quad full high definition) resolution are provided and applied to the image encoding/decoding environment of the H.264/AVC image encoding standard of the QFHD resolution and the effective dictionary base compression and de-compression algorithm, the image data compression rate can be tremendously raised at the resolution of 1080 HD (High Definition) content and the average memory data rate is greatly decreased. Hence only a bus with a lower frequency as 57 MHz can be done for the real-time of the resolution of 1080 HD content.

Abstract: A decoding method of CABAC is proposed. A CABAC decoder comprises an arithmetic engine performing two arithmetic decodings for a coefficient or reading contexts at the same time in a clock cycle. The arithmetic decoding for a coefficient comprises the steps of: (1) providing a residual block comprising Significant_flags, Last_significant_flags, coefficients and the corresponding contexts; (2) sequentially resolving the Significant_flag and the Last_significant_flag of a non-zero coefficient; and (3) decoding the non-zero coefficient to obtain regular bins and bypass bins, wherein the arithmetic decoding is conducted twice in a clock cycle.

Abstract: A so-called inter-macroblock parallelism is proposed for motion estimation. First, pixel data of one of the consecutive candidate blocks in an overlapped region of search windows of current blocks in a reference frame including reference blocks corresponding to the current blocks are read and transferred to a plurality of processing element (PE) arrays in parallel. The plurality of PE arrays are used to determine the match situation of the current blocks and the reference blocks. Then, the above process is repeated for the rest of the candidate blocks in sequence. For example, if there are four current blocks CB1-CB4 and four consecutive candidate blocks, at the beginning the data of the first candidate block are read and transferred to four PE arrays in parallel, and so to the second, third and fourth candidate blocks in sequence, and the four PE arrays calculate SADs for CB1 to CB4, respectively.