Patents by Inventor Youn-seok Jeong
Youn-seok Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9578396Abstract: Disclosed are a method and a device for providing a hypertext markup language (HTML)-based program guide service, and a recording medium therefor. The method for providing a hypertext markup language (HTML)-based program guide service in a broadcast providing device, according to the present invention, comprises the steps of: outputting a start page according to a program guide service start request of a user, wherein a container included in a resource for the start page generates a first key handler for processing a key event of the user; and outputting one or more menu pages for menu navigation according to a request of the user, wherein the start page and each of the one or more menu pages have different resource addresses, and a life cycle of the one or more menu pages is managed by the first key handler.Type: GrantFiled: March 25, 2015Date of Patent: February 21, 2017Assignee: Alticast CorporationInventors: Youn Seok Jeong, Jin Won Lee, Sang Yong Kim
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Publication number: 20150201251Abstract: Disclosed are a method and a device for providing a hypertext markup language (HTML)-based program guide service, and a recording medium therefor. The method for providing a hypertext markup language (HTML)-based program guide service in a broadcast providing device, according to the present invention, comprises the steps of: outputting a start page according to a program guide service start request of a user, wherein a container included in a resource for the start page generates a first key handler for processing a key event of the user; and outputting one or more menu pages for menu navigation according to a request of the user, wherein the start page and each of the one or more menu pages have different resource addresses, and a life cycle of the one or more menu pages is managed by the first key handler.Type: ApplicationFiled: March 25, 2015Publication date: July 16, 2015Inventors: YOUN SEOK JEONG, Jin Won Lee, Sang Yong Kim
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Patent number: 7825459Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.Type: GrantFiled: April 30, 2009Date of Patent: November 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-hyung Kim, Chung-woo Kim, Soo-doo Chae, Youn-seok Jeong
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Publication number: 20090238004Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.Type: ApplicationFiled: April 30, 2009Publication date: September 24, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-hyung Kim, Chung-woo Kim, Soo-doo Chae, Youn-seok Jeong
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Patent number: 7531870Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.Type: GrantFiled: July 23, 2007Date of Patent: May 12, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-hyung Kim, Chung-woo Kim, Soo-doo Chae, Youn-seok Jeong
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Patent number: 7349262Abstract: A method of programming a silicon oxide nitride oxide semiconductor (SONOS) memory device is provided. The SONOS memory device includes a substrate, first and second impurity regions spaced apart on the substrate, a gate oxide layer formed over the substrate between the first and second impurity regions, a trap layer formed over the gate oxide layer, an insulation layer formed over the trap layer, and a gate electrode formed over the insulation layer. The method of programming the SONOS device includes writing data into the SONOS memory device by applying a first voltage to the first impurity region, a gate voltage to the gate electrode, and a second voltage to the second impurity region, where the second voltage is a negative voltage.Type: GrantFiled: May 12, 2006Date of Patent: March 25, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Youn-seok Jeong, Chung-woo Kim, Hee-soon Chae, Ju-hyung Kim, Jeong-hee Han, Jae-woong Hyun
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Publication number: 20070267688Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.Type: ApplicationFiled: July 23, 2007Publication date: November 22, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-hyung Kim, Chung-woo Kim, Soo-doo Chae, Youn-seok Jeong
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Patent number: 7250653Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.Type: GrantFiled: May 20, 2004Date of Patent: July 31, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-hyung Kim, Chung-woo Kim, Soo-doo Chae, Youn-seok Jeong
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Publication number: 20060291286Abstract: A method of programming a silicon oxide nitride oxide semiconductor (SONOS) memory device is provided. The SONOS memory device includes a substrate, first and second impurity regions spaced apart on the substrate, a gate oxide layer formed over the substrate between the first and second impurity regions, a trap layer formed over the gate oxide layer, an insulation layer formed over the trap layer, and a gate electrode formed over the insulation layer. The method of programming the SONOS device includes writing data into the SONOS memory device by applying a first voltage to the first impurity region, a gate voltage to the gate electrode, and a second voltage to the second impurity region, where the second voltage is a negative voltage.Type: ApplicationFiled: May 12, 2006Publication date: December 28, 2006Inventors: Youn-seok Jeong, Chung-woo Kim, Hee-soon Chae, Ju-hyung Kim, Jeong-hee Han, Jae-woong Hyun
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Publication number: 20060255399Abstract: Provided is a nonvolatile memory device which includes a tunneling insulating film formed on a semiconductor substrate, a storage node formed on the tunneling insulating film, a blocking insulating film formed on the storage node, and a control gate electrode formed on the blocking insulating film. The storage node includes at least two trapping films having different trap densities, and the blocking insulating film has a dielectric constant greater than that of the silicon oxide film.Type: ApplicationFiled: February 15, 2006Publication date: November 16, 2006Inventors: Ju-Hyung Kim, Jeong-Hee Han, Chung-Woo Kim, Yo-Sep Min, Moon-Kyung Kim, Youn-Seok Jeong
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Publication number: 20060186462Abstract: Provided are example embodiments of fabrication methods and resulting structures suitable for use in nonvolatile memory devices formed on semiconductor substrates. The example embodiments of the gate structures include a first insulating film formed on the semiconductor substrate, a storage node formed on the first insulating film for storing charges, a second insulating film formed on the storage node, a third insulating film formed on the second insulating film, and a gate electrode formed on the third insulating film. The insulating films are selected whereby the dielectric constant of one or both of the second and third insulating films is greater than the dielectric constant of the first insulating film.Type: ApplicationFiled: February 21, 2006Publication date: August 24, 2006Inventors: Jeong-Hee Han, Ju-Hyung Kim, Chung-Woo Kim, Sang-Hun Jeon, Youn-Seok Jeong, Seung-Hyun Lee
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Publication number: 20040232478Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.Type: ApplicationFiled: May 20, 2004Publication date: November 25, 2004Inventors: Ju-hyung Kim, Chung-woo Kim, Soo-doo Chae, Youn-seok Jeong