Abstract: An apparatus for manufacturing a semiconductor device includes a substrate transfer unit configured to transfer a substrate, a rail unit including a driving rail extending in a first direction that the substrate transfer unit moves and a stopper on a side of the driving rail in a second direction crossing the first direction, and a lifting unit configured to move in the first direction and a third direction perpendicular to the first and second directions to remove the substrate transfer unit from the rail unit, wherein the lifting unit is configured to contact the stopper to move the stopper from a closed state to an open state.

Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

Abstract: A device for verifying a circuit design including a first circuit block and a second circuit block includes a verification vector generator and a design verifier. The verification vector generator determines a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block. The design verifier performs design verification for the first circuit block by using the first verification vector.

Abstract: A device for verifying a circuit design including a first circuit block and a second circuit block includes a verification vector generator and a design verifier. The verification vector generator determines a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block. The design verifier performs design verification for the first circuit block by using the first verification vector.

Abstract: A crane for loading and unloading a cargo includes multi-stage trolley. The multi-stage trolley for a crane includes a first trolley movable in a longitudinal direction along a boom of the crane; a second trolley movable in a lateral direction on the first trolley; a hoisting wire provided in the longitudinal direction along the boom; a spreader connected to the hoisting wire through the first trolley and the second trolley and supported by the hoisting wire, the spreader being movable in a vertical direction according to a movement of the hoisting wire. The multi-stage trolley further includes a sheave block unit for changing a direction of the hoisting wire to maintain a vertical level of the spreader constant when the first trolley and/or the second trolley is moved.

Abstract: Provided is a three-wheeled electric vehicle. The three-wheeled electric vehicle includes: a front left wheel disposed on a front left portion of the three-wheeled electric vehicle; a front right wheel disposed on a front right portion of the three-wheeled electric vehicle; a rear wheel disposed on a rear center portion of the three-wheeled electric vehicle; a first driving motor configured to transfer a driving power to the front left wheel; a second driving motor configured to transfer a driving power to the front right wheel; and a steering motor configured to transfer a steering power to the rear wheel.

Abstract: A crane for loading and unloading a cargo includes multi-stage trolley. The multi-stage trolley for a crane includes a first trolley movable in a longitudinal direction along a boom of the crane; a second trolley movable in a lateral direction on the first trolley; a hoisting wire provided in the longitudinal direction along the boom; spreader connected to the hoisting wire through the first trolley and the second trolley and supported by the hoisting wire, the spreader being movable in a vertical direction according to a movement of the hoisting wire. The multi-stage trolley further includes a sheave block unit for changing a direction of the hoisting wire to maintain a vertical level of the spreader constant when the first trolley and/or the second trolley is moved.

Abstract: A latency signal generator and method thereof are provided. The example latency signal generator may include a sampling clock signal generator adjusting a plurality of initial sampling clock signals based on a received clock signal to generate a plurality of adjusted sampling clock signals, a latch enable signal supply unit adjusting a plurality of initial latch enable signals based on a given one of the plurality of initial sampling clock signals to generate a plurality of adjusted latch enable signals and a latch unit including a plurality of latency latches, each of the plurality of latency latches selectively latching a given internal read command based on one of the plurality of adjusted sampling clock signals and one of the plurality of adjusted latch enable signals.

Abstract: A latency signal generator and method thereof are provided. The example latency signal generator may include a sampling clock signal generator adjusting a plurality of initial sampling clock signals based on a received clock signal to generate a plurality of adjusted sampling clock signals, a latch enable signal supply unit adjusting a plurality of initial latch enable signals based on a given one of the plurality of initial sampling clock signals to generate a plurality of adjusted latch enable signals and a latch unit including a plurality of latency latches, each of the plurality of latency latches selectively latching a given internal read command based on one of the plurality of adjusted sampling clock signals and one of the plurality of adjusted latch enable signals.

Abstract: Disclosed herein is a multi-cantilever MEMS sensor functioning as a mechanical sensor having a plurality of cantilevers, replacing a conventional DSP based sound source localization algorithm and reducing production cost when the MEMES sensor applied to mass-produced robots, a manufacturing method thereof, a sound source localization apparatus using the multi-cantilever MEMS sensor and a sound source localization method using the sound source localization apparatus.

Abstract: A semiconductor memory device and methods thereof are provided. The example semiconductor memory device may include an internal address generating circuit operating in accordance with a first addressing protocol during normal operation and operating in accordance with a second addressing protocol during a test operation, the first addressing protocol associated with a first number of clock cycles for transferring a memory address and the second addressing protocol associated with a second number of clock cycles for transferring a memory address, the first number of clock cycles being greater than the second number of clock cycles.

Abstract: A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

Abstract: In an example embodiments, a single signal-to-differential signal converter includes a first inverter for receiving and inverting a single input signal and outputting an inverted single input signal to a first node, and a first differential signal generating portion for generating a first signal and an inverted first signal which have the opposite phases to each other to second and third nodes in response to the single input signal.

Abstract: Disclosed herein is a multi-cantilever MEMS sensor functioning as a mechanical sensor having a plurality of cantilevers, replacing a conventional DSP based sound source localization algorithm and reducing production cost when the MEMES sensor applied to mass-produced robots, a manufacturing method thereof, a sound source localization apparatus using the multi-cantilever MEMS sensor and a sound source localization method using the sound source localization apparatus.

Abstract: A synchronous semiconductor memory device includes an output control signal generator, which generates an output control signal corresponding to a signal obtained by delaying a read information signal in response to a delay internal clock signal obtained by dividing an internal clock signal by n, first and second sampling signals obtained by delaying the internal clock signal, a first output control clock signal obtained by dividing the internal clock signal by n, and a column address strobe (CAS) latency signal. The synchronous semiconductor memory device also includes a data output buffer, which outputs data by buffering internal data in response to the output control signal and the first output control clock signal.

Abstract: In an example embodiments, a single signal-to-differential signal converter includes a first inverter for receiving and inverting a single input signal and outputting an inverted single input signal to a first node, and a first differential signal generating portion for generating a first signal and an inverted first signal which have the opposite phases to each other to second and third nodes in response to the single input signal.

Abstract: A semiconductor memory device and an arrangement method thereof are included. The semiconductor memory device includes column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

Abstract: A semiconductor memory device and methods thereof are provided. The example semiconductor memory device may include an internal address generating circuit operating in accordance with a first addressing protocol during normal operation and operating in accordance with a second addressing protocol during a test operation, the first addressing protocol associated with a first number of clock cycles for transferring a memory address and the second addressing protocol associated with a second number of clock cycles for transferring a memory address, the first number of clock cycles being greater than the second number of clock cycles.