Patents by Inventor Youn Soo Choi

Youn Soo Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240095963
    Abstract: Disclosed herein are a method, apparatus, and storage medium for image encoding/decoding. Selective compression learning of latent representations for variable-rate image compression is used for the method, apparatus, and storage medium. A selective compression method that partially encodes latent representations in a completely generalized manner for deep-learning-based variable-rate image compression is disclosed in embodiments. The methods of the embodiments adaptively determine essential representation elements for compression at different target quality levels.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 21, 2024
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Jooyoung LEE, Se-Yoon JEONG, Youn-Hee KIM, Jin-Soo CHOI
  • Publication number: 20240078710
    Abstract: Disclosed herein are a method, an apparatus and a storage medium for encoding/decoding using a transform-based feature map. An optimal basis vector is extracted from one or more feature maps, and a transform coefficient is acquired through a transform using the basis vector. The basis vector and the transform coefficient may be transmitted through a bitstream. In an embodiment, one or more feature maps are reconstructed using the basis vector and the transform coefficient, which are decoded from the bitstream.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 7, 2024
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Youn-Hee KIM, Jooyoung LEE, Se-Yoon JEONG, Jin-Soo CHOI, Dong-Gyu SIM, Na-Seong KWON, Seung-Jin PARK, Min-Hun LEE, Han-Sol CHOI
  • Patent number: 7833813
    Abstract: The present invention provides a method of manufacturing a TFT array panel in a cost-effective manner. The method includes: forming thin film transistors each having a gate electrode, a source electrode, and a drain electrode; forming an insulating layer on the thin film transistors; forming a first conductive layer electrically connected to the drain electrodes on the insulating layer; forming a second conductive layer on the first conductive layer; forming a photoresist layer including first portions and second portions thinner than the first portions; selectively etching the second conductive layer with a first etchant by using the photoresist layer as an etch blocker; and selectively etching the first conductive layer with a second etchant by using the photoresist layer and the second conductive layer as etch blockers.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: November 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Neung-Ho Cho, Sung-Wook Kim, Yong-Kil Park, Bae-Hyoun Jung, Dong-Yub Chae, Youn-Soo Choi
  • Publication number: 20070019122
    Abstract: A substrate for an LCD display device exhibiting improved display quality through lower contact resistance and elimination of undercutting. The display switches have three electrodes, at least one of which has three metal layers, the third of which is formed by nitrating the second metal layer. The pixel electrode is electrically connected to the second metal layer through a contact hole formed through an insulation layer and the second metal layer of the switching device.
    Type: Application
    Filed: July 20, 2006
    Publication date: January 25, 2007
    Inventors: In-Sung Lee, Neugng-Ho Cho, Dong-Hoon Lee, Youn-Soo Choi, Ho-Geun Choi, Jin-Chel Choi
  • Publication number: 20070020836
    Abstract: A method for manufacturing a TFT substrate includes forming a gate metal layer on an insulating substrate, forming a photo-sensitive layer pattern on the gate metal layer, forming a gate wiring by etching the gate metal layer using the photo-sensitive layer pattern, exposing the gate wiring by stripping the photo-sensitive layer pattern, and washing exposed gate wiring with a washing agent containing nitric acid. Thus, the present invention provides a method for manufacturing a TFT substrate to improve the quality of the thin metal layer by removing particles effectively.
    Type: Application
    Filed: May 18, 2006
    Publication date: January 25, 2007
    Inventors: Dong-won Moon, Deuck-soo Lim, Youn-soo Choi, Ho-geun Choi
  • Publication number: 20060160260
    Abstract: The present invention provides a method of manufacturing a TFT array panel in a cost-effective manner. The method includes: forming thin film transistors each having a gate electrode, a source electrode, and a drain electrode; forming an insulating layer on the thin film transistors; forming a first conductive layer electrically connected to the drain electrodes on the insulating layer; forming a second conductive layer on the first conductive layer; forming a photoresist layer including first portions and second portions thinner than the first portions; selectively etching the second conductive layer with a first etchant by using the photoresist layer as an etch blocker; and selectively etching the first conductive layer with a second etchant by using the photoresist layer and the second conductive layer as etch blockers.
    Type: Application
    Filed: January 20, 2006
    Publication date: July 20, 2006
    Inventors: Neung-Ho Cho, Sung-Wook Kim, Yong-Kil Park, Bae-Hyoun Jung, Dong-Yub Chae, Youn-Soo Choi
  • Patent number: 6704962
    Abstract: Disclosed are an elastic body having a good elasticity and an impact absorbing efficiency, a method of manufacturing the same and a mattress employing the same. The elastic body is a foamed polyurethane body including polystyrene and has a plurality of foams in which air is contained. The elastic body is prepared by a method comprising the steps of preparing polyether polyol by mixing poly alcohol and a polyether compound in a mixing ratio of 3-5 to 5-7 by weight, obtaining a polyol mixture by adding 2-20 parts by weight of polystyrene and a trace amount of a catalyst and water to 30-50 parts by weight of the obtained polyether polyol, adding and stirring 20-60 parts by weight of an isocyanate compound to 40-80 parts by weight of the polyol mixture at 20-80° C., and pouring the resulting product into a mold to foam cast. A mattress manufactured by using such elastic bodies has a good elasticity and is capable of absorbing pressure, thereby providing comfort for users.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: March 16, 2004
    Inventor: Youn Soo Choi
  • Publication number: 20030101517
    Abstract: Disclosed are an elastic body having a good elasticity and an impact absorbing efficiency, a method of manufacturing the same and a mattress employing the same. The elastic body is a foamed polyurethane body including polystyrene and has a plurality of foams in which air is contained. The elastic body is prepared by a method comprising the steps of preparing polyether polyol by mixing poly alcohol and a polyether compound in a mixing ratio of 3-5 to 5-7 by weight, obtaining a polyol mixture by adding 2-20 parts by weight of polystyrene and a trace amount of a catalyst and water to 30-50 parts by weight of the obtained polyether polyol, adding and stirring 20-60 parts by weight of an isocyanate compound to 40-80 parts by weight of the polyol mixture at 20-80° C., and pouring the resulting product into a mold to foam cast. A mattress manufactured by using such elastic bodies has a good elasticity and is capable of absorbing pressure, thereby providing comfort for users.
    Type: Application
    Filed: January 2, 2002
    Publication date: June 5, 2003
    Inventor: Youn Soo Choi