Abstract: This application is directed to methods and devices of detecting and correcting a fault in an integrated circuit. A latching circuit outputs a first voltage level at an output, and a function control signal is generated to hold the first voltage level outputted by the latching circuit. A single event upset originates within the latching circuit and causes the first voltage level at the output of the latching circuit to transition to a second voltage level. When the single event upset is detected, the latching circuit is controlled via a clear signal to reset its output to the first voltage level. A glitch is thereby formed on the first voltage level at the output of the latching circuit. The glitch is suppressed at the output of the latching circuit to generate the function control signal holding the first voltage level without the glitch.

Abstract: This application is directed to methods and devices of detecting and correcting a fault in an integrated circuit. A latching circuit outputs a first voltage level at an output, and a function control signal is generated to hold the first voltage level outputted by the latching circuit. A single event upset originates within the latching circuit and causes the first voltage level at the output of the latching circuit to transition to a second voltage level. When the single event upset is detected, the latching circuit is controlled via a clear signal to reset its output to the first voltage level. A glitch is thereby formed on the first voltage level at the output of the latching circuit. The glitch is suppressed at the output of the latching circuit to generate the function control signal holding the first voltage level without the glitch.

Abstract: This application is directed to methods and devices of detecting and correcting a fault in an integrated circuit. A latching circuit outputs a first voltage level at an output, and a function control signal is generated to hold the first voltage level outputted by the latching circuit. A single event upset originates within the latching circuit and causes the first voltage level at the output of the latching circuit to transition to a second voltage level. When the single event upset is detected, the latching circuit is controlled via a clear signal to reset its output to the first voltage level. A glitch is thereby formed on the first voltage level at the output of the latching circuit. The glitch is suppressed at the output of the latching circuit to generate the function control signal holding the first voltage level without the glitch.

Abstract: This application is directed to methods and devices of detecting and correcting a fault in an integrated circuit. A latching circuit outputs a first voltage level at an output, and a function control signal is generated to hold the first voltage level outputted by the latching circuit. A single event upset originates within the latching circuit and causes the first voltage level at the output of the latching circuit to transition to a second voltage level. When the single event upset is detected, the latching circuit is controlled via a clear signal to reset its output to the first voltage level. A glitch is thereby formed on the first voltage level at the output of the latching circuit. The glitch is suppressed at the output of the latching circuit to generate the function control signal holding the first voltage level without the glitch.

Abstract: A voltage-controlled oscillator (VCO) capable of controlling VCO gain magnitude, VCO frequency tuning range and gain linearity, which in turn allows the loop bandwidth of a phase-locked loop to be controlled electrically with the VCO circuit and increases the frequency tuning range for the VCO circuit. An embodiment includes a voltage-controlled oscillator comprising an LC tank having a plurality of varactors, each of the plurality of varactors having four terminals. At least one of the terminals is coupled to a first control signal and one of the terminals is a substrate terminal coupled to a second control signal.

Abstract: A memory and a method for communicating therewith are implemented having a unidirectional write bus for writing to memory cells within a plurality of memory cell groups. Local bitlines associated with each of the memory cell groups communicate write data to the associated memory cell. Global bitlines coupled to all of the memory cells are decoupled from the local bitlines during a write operation. Following a write operation the local bitlines are restored by a precharge operation during which the global and local bitlines are also decoupled.

Abstract: A memory and a method for communicating therewith are implemented having a unidirectional write bus for writing to memory cells within a plurality of memory cell groups. Local bitlines associated with each of the memory cell groups communicate write data to the associated memory cell. Global bitlines coupled to all of the memory cells are decoupled from the local bitlines during a write operation. Following a write operation the local bitlines are restored by a precharge operation during which the global and local bitlines are also decoupled.

Abstract: A memory cell with multiple read ports uses fewer NMOS devices, has reduced size, and provides improved performance if less than all of the read ports are used. The memory cell has a flip-flop with a storage node, a write port, and a read port having a plurality of bit lines connected to respective NMOS transistors which are controlled by respective read wordlines, and these NMOS transistors are coupled to ground via one or more additional NMOS transistor whose gates are connected to the storage node. The width of the latter NMOS transistors is larger than the width of the former transistors which are connected to the bit lines. For example, there might be three bitlines connected respectively to three of the first NMOS transistors, which are further connected to only one second NMOS transistor, wherein the second NMOS transistor is about three times as wide as any one of the three first NMOS transistors.

Abstract: A memory and a method for communicating therewith are implemented, the memory having a plurality of memory cell groups. Each memory cell group contains a plurality of memory cells. Memory cell groups within each subset of a plurality of subsets of memory cell groups include the same predetermined number of memory cells. During a read operation, a local bitline associated with the memory cell group from which data is being read is coupled to a global bitline. Other local bitlines, associated with the memory cell groups not being accessed during the read are decoupled from the global bitlines. Following a read, the local and global bitlines are restored by a precharge operation.

Abstract: A sense amplifier with improved compensation for clock skew effects is provided and includes a sense amplifier enabling mechanism for receiving first and second control signals. The sense amplifier further includes a first logic mechanism for providing the first control signal to a first input of the sense amplifier enabling mechanism, and a second logic mechanism for providing the second control signal to a second input of the sense amplifier enabling mechanism, wherein the first and second logic mechanisms reduce speed degradation by minimizing skew between the first and second control signals. In a method aspect, a method for reducing speed degradation in a sense amplifier includes providing a pull down device, and coupling the pull down device to first and second signal paths, the first signal path propagating a first clock signal and the second signal path propagating a second clock signal, for reducing speed degradation resulting from skew between the first and second clock signals.

Abstract: An improved decoder apparatus and method for memory-array read operations are presented. The improved decoder apparatus includes a number of row decoder circuits such that each row decoder circuit includes a footed domino circuit having a pull-down device located within a pull-down path of the footed domino circuit. The improved decoder apparatus further includes a common shared node coupled to each pull-down device such that the shared common node allows the pull-down strength of each pull-down device to be increased proportionally to the number of row decoder circuits which share the common shared node, thereby promoting increased decoding operational rates and faster memory-array read operations. The pull-down device can be an N-type pull-down device. In addition, each row decoder circuit includes an address predecoder, coupled to the footed domino circuit, that receives a number of address inputs and combines address inputs into a single digital signal for utilization by the improved decoder apparatus.

Abstract: A method and apparatus that controls and modulates the amount of hysteresis in a buffer in response to changes in operating conditions. The buffer comprises a first stage switching element and a hysteresis control element. The first stage switching element is configured to have a DC voltage trip point. As an input voltage, transitioning from a first state to a second state, is applied to the first stage switching element, the first stage switching element transitions as the input voltage reaches the DC voltage trip point. The transition of the first stage switching element enables the hysteresis control element to provide a feedback path biasing the first stage switching element. Consequently, as the input voltage transitions from the second logic level to the first logic level, the first stage switching element transitions at a voltage level offset from the DC trip point to provide hysteresis in the buffer.