Abstract: An image sensor includes at least two pixels and a control circuit. The control circuit is configured to provide a first modulation voltage and a second modulation voltage having a phase difference of 180 degrees from each other to each of the at least two pixels in a first mode. The control circuit is also configured to provide the first modulation voltage to a first pixel among the at least two pixels and provide the second modulation voltage to a second pixel among the at least two pixels in a second mode.

Abstract: Disclosed herein is a device including a driving thin film transistor. The driving thin film transistor includes a metal oxide channel, a source electrode in contact with the driving metal oxide channel, and a top gate electrode disposed above the metal oxide channel and physically connected to the driving source electrode.

Abstract: A processor implement method may include determining a target azimuth angle of the target object based on an initial radar signal received through an array antenna of a radar sensor, generating a correction radar signal by correcting a phase of the initial radar signal based on the target azimuth angle, and determining an elevation angle of the target object based on the correction radar signal.

Abstract: A coil component includes a body, a support member, a first coil including a first coil portion disposed on one surface of the support member and having one end and the other end being a first lead-out portion and a first connection portion, respectively, a sub-lead-out portion disposed on the other surface of the support member, and a first via connecting the first lead-out portion and the sub-lead-out portion, a second coil disposed on the other surface of the support member and including a second coil portion having one end and the other end being a second lead-out portion and a second connection portion, respectively, and a second via connecting the first and second connection portions, wherein the first via has a diameter greater than a diameter of the second via.

Abstract: Methods and systems for determining a Pulse Repetition Frequency (PRF) pattern of a Secondary Surveillance Radar (SSR) are disclosed, when an ownship aircraft is not being able to receive interrogation signals from the SSR. Instead, a transponder equipped opportunistic aircraft with Automatic Dependent Surveillance-Broadcast (ADS-B) Out functionality is used, which is in the line-of-sight with both the SSR and the ownship aircraft. The opportunistic aircraft is interrogated during one or more rotations of the SSR, when within a beam of the SSR. At the ownship, the transponder response signals from the opportunistic aircraft are collected, and the position of the opportunistic aircraft is decoded from ADS-B Out messages. The PRF of the SSR is determined using the collected transponder response signals, the decoded position of the opportunistic aircraft, a position of the ownship and a position of the SSR, and a predetermined transponder response time at the opportunistic aircraft.

Abstract: A multilayer ceramic capacitor includes a body including a capacitance region in which a plurality of first internal electrodes and a plurality of second internal electrodes are alternately stacked in a first direction with a dielectric layer interposed therebetween, and first and second external electrodes disposed on the body and spaced apart from each other to be connected to the plurality of first internal electrodes and the plurality of second internal electrodes, respectively, wherein the capacitance region includes one or more groups of first openings. The first openings in each group overlap in the first direction and are continuously open in two or more internal electrodes of the plurality of first and second internal electrodes, and a number of internal electrodes included in each group is less than a total number of the plurality of first internal electrodes and the plurality of second internal electrodes.

Abstract: A computational network interface card (NIC) sharing a storage space with a memory expander thereof includes: a NIC memory including instructions; a NIC processor including a cache and electrically connected to the NIC memory; and a NIC configured to transmit data stored in the NIC memory or the cache to a network, wherein, the instructions are configured to cause the NIC processor to perform operations including: receiving a request to read or write metadata; and checking whether the requested metadata is stored in a local metadata cache of the computational NIC by sequentially checking whether the metadata is stored in the cache of the NIC processor, a cache of the NIC, the NIC memory, or the memory expander.

Abstract: Provided is an apparatus for processing a substrate, the apparatus including: a chamber having a processing space; a support unit for supporting a substrate in the processing space; a gas supply unit for supplying process gas to the processing space; and a plasma generation unit for generating plasma from the process gas, in which the plasma generation unit includes: an inner coil part including a plurality of inner coils; an outer coil part provided to surround the inner coil part when viewed from above and including a plurality of outer coils; an upper power source for applying power to the inner coil part and the outer coil part, and a ground plate disposed above the inner coil part and the outer coil part and grounding the inner coil part and the outer coil part.

Abstract: Methods and systems using unique item identifiers and a wireless device to (a) authenticate authorization to take possession of an item and (b) specifying and/or tracking service processing of the item.

Abstract: A semiconductor structure is presented having a plurality of circuit rows, a plurality of first power rails positioned on front sides of the plurality of circuit rows, a plurality of second power rails positioned on back sides of the plurality of circuit rows, and power tap cells associated with each the plurality of circuit rows, wherein each of the power tap cells includes one or more power vias connecting at least one first power rail of the plurality of first power rails to at least one second power rail of the plurality the second power rails. In one instance, the plurality of second power rails are orthogonal to the plurality of first power rails. in another instance, the plurality of first power rails are horizontally offset from the plurality of second power rails. The one or more power vias include at least two or more different sized power vias.

Abstract: Disclosed is a non-destructive inspection method capable of effectively evaluating adhesion quality of an adhesion portion formed between a cell frame and an EGA without damage to parts or deterioration in durability or adhesiveness of parts. In addition, an EGA-cell frame assembly capable of effectively evaluating adhesion quality of an adhesion portion formed between a cell frame and an EGA by the non-destructive inspection method is provided.

Abstract: Provided is a semiconductor chip stack structure including a plurality of first semiconductor chip dies stacked in a vertical direction, and one or more second semiconductor chip dies between adjacent first semiconductor chip dies among the plurality of first semiconductor chip dies, wherein a thickness of each second semiconductor chip die of the one or more second semiconductor chip dies is greater than a thickness of each first semiconductor chip die of the plurality of first semiconductor chip dies in the vertical direction.

Abstract: A display device includes a first area, a second area, and a bending area between the first area and the second area, a light emitting element, an inorganic layer disposed on the light emitting element, and a thin film encapsulation layer disposed on the inorganic layer. The inorganic layer includes a first inorganic pattern in the bending area.

Abstract: Apparatus, methods, and articles of manufacture or disclosed for implementing risk scoring systems used for vulnerability mitigation in a distributed computing environment. In one disclosed example, a computer-implemented method of mitigating vulnerabilities within a computing environment includes producing a risk score indicating at least one of: a vulnerability component, a security configuration component, or a file integrity component for an object within the computing environment, producing a signal score indicating a factor that contributes to risk for the object, and combining the risk score and the signal score to produce a combined risk score indicating a risk level associated with at least one vulnerability of the computing system object. In some examples, the method further includes mitigating the at least one vulnerability by changing a state of a computing object using the combined risk score.

Abstract: A method for execution by a computer generating a virtual reality environment utilizing a group of object representations by identifying an exclusion asset and modifying a set of common illustrative assets to exclude the exclusion asset to produce a redacted set of common illustrative assets. The method further includes rendering a portion of the redacted set of common illustrative asset to produce a redacted set of common illustrative asset video frames and selecting a subset of the redacted set of common illustrative asset video frames to produce a common portion of video frames for the virtual reality environment. The method further includes rendering representations of object representations to produce remaining portions of the video frames for the virtual reality environment. The method further includes linking the common portion and the remaining portions of the video frames to produce the virtual reality environment for interactive consumption.

Abstract: A memory device includes a memory cell array having a plurality of memory blocks therein, including a target memory block. A voltage generator is provided, which is configured to generate an erase voltage and row line voltages, which are provided to the target memory block upon which an erase operation is to be performed. Control logic is provided, which is configured to control the memory cell array and the voltage generator. In addition, during operation, the erase voltage is provided to at least one of a bitline or a common source line associated with the target memory block, and a gate line of a transistor provided with the erase voltage is precharged before the erase voltage is provided to the at least one of the bitline or the common source line of the target memory block.

Abstract: The present disclosure relates to a display apparatus and control method thereof. The display apparatus includes a receiver configured to receive input image data, an accumulator configured to generate a cumulative data count by analyzing a degree of degradation according to the received input image data and a burn-in factor, an interpolator configured to update the cumulative data count in a memory by applying an adaptive weight to the generated cumulative data count, and a compensator configured to generate compensation data using the input image data and the updated cumulative data count.

Abstract: The present invention may provide a motor comprising: a shaft; a rotor coupled to the shaft; a stator disposed so as to correspond to the rotor; a bearing supporting the shaft; and a bearing housing supporting the bearing. The bearing housing comprises: a first groove where the shaft is disposed; a first surface and a second surface constituting the outer surface of the bearing housing, the first surface contacting the inner circumferential surface of an inner race of the bearing, and the second surface contacting one surface of the inner race of the bearing; and a second groove disposed in the bottom surface of the first groove.

Abstract: The present invention relates to a method for calibrating a data set of a target analyte in a sample, wherein a normalization coefficient for calibrating the data set is provided by using a reflective value, a reference cycle and the data set, and the calibrated data set is obtained by applying the normalization coefficient to the signal values of the data set. The present method is very effective in removing the inter- and intra-instrument signal values of data sets. Furthermore, since the present method can be configured in software, the instant method is capable of being applied universally to various analytical instruments (e.g., a real-time PCR instruments) regardless of manufacture. Accordingly, the method by the present invention would be very useful in diagnostic data analysis.

Abstract: A semiconductor device includes an active pattern on a substrate, source/drain patterns on the active pattern, channel patterns on the active pattern and connected to the source/drain patterns each including stacked semiconductor patterns, gate electrodes on the channel patterns and extending in parallel to each other in a first direction, and a power line adjacent to the active pattern. The power line extends in a second direction. The active pattern includes a first region having a first width, a second region having a second width, and a third region between the first and second regions. The first region has a first sidewall extending in the second direction. The second region has a second sidewall extending in the second direction. The third region has a recessed sidewall that connects the first and second sidewalls. The recessed sidewall is recessed toward the power line.