Patents by Inventor Young Bang Lee
Young Bang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240076127Abstract: Provided is a ceiling storage system capable of correcting a working position and constantly checking stability of a structure by detecting an amount of change in a facility. According to the ceiling storage system, a transport vehicle moves to an upper portion of a first storage area of a plurality of storage areas in a state of gripping an article, and the transport vehicle measures a first distance value between the transport vehicle and the first storage area using a distance sensor and measures a relative position value between the transport vehicle and the first storage area using a vision sensor, before unloading the article from the first storage area.Type: ApplicationFiled: May 23, 2023Publication date: March 7, 2024Inventors: Sang Kyung LEE, Seung Gyu KANG, Hyun Jae KANG, Young Wook KIM, Sang A BANG, Yong-Jun AHN, Min Kyun LEE, Hyun Woo LEE, Jeong Hun LIM, Jun Hyuk CHANG
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Patent number: 9520459Abstract: A surface treatment method for a semiconductor device includes providing a substrate where a plurality of projected patterns are formed, forming a hydrophobic coating layer on a surface of each of the plurality of projected patterns, rinsing the substrate with deionized water, and drying the substrate, wherein the hydrophobic coating layer is formed using a coating agent that includes phosphate having more than one hydrocarbon group, phosphonate having more than one hydrocarbon group, or a mixture thereof.Type: GrantFiled: February 19, 2016Date of Patent: December 13, 2016Assignee: SK Hynix Inc.Inventors: Sung-Hyuk Cho, Hyo-Sang Kang, Sung-Ki Park, Kwon Hong, Hyung-Soon Park, Hyung-Hwan Kim, Young-Bang Lee, Ji-Hye Han, Tae-Yeon Jung, Hyeong-Jin Nor
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Publication number: 20160172433Abstract: A surface treatment method for a semiconductor device includes providing a substrate where a plurality of projected patterns are formed, forming a hydrophobic coating layer on a surface of each of the plurality of projected patterns, rinsing the substrate with deionized water, and drying the substrate, wherein the hydrophobic coating layer is formed using a coating agent that includes phosphate having more than one hydrocarbon group, phosphonate having more than one hydrocarbon group, or a mixture thereof.Type: ApplicationFiled: February 19, 2016Publication date: June 16, 2016Inventors: Sung-Hyuk CHO, Hyo-Sang KANG, Sung-Ki PARK, Kwon HONG, Hyung-Soon PARK, Hyung-Hwan KIM, Young-Bang LEE, Ji-Hye HAN, Tae-Yeon JUNG, Hyeong-Jin NOR
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Patent number: 8841198Abstract: An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer is formed in the trench including the first liner nitride layer. The flowable insulation layer is formed such to define a recess in the trench. A second liner nitride layer is formed on the recess including the flowable insulation layer and the first liner nitride layer. Finally, an insulation layer is formed in the recess on the second liner nitride layer to completely fill the trench.Type: GrantFiled: July 3, 2008Date of Patent: September 23, 2014Assignee: Hynix Semiconductor Inc.Inventors: Hyung Hwan Kim, Kwang Kee Chae, Jong Goo Jung, Ok Min Moon, Young Bang Lee, Sung Eun Park
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Publication number: 20140179118Abstract: A surface treatment method for a semiconductor device includes providing a substrate where a plurality of projected patterns are formed, forming a hydrophobic coating layer on a surface of each of the plurality of projected patterns, rinsing the substrate with deionized water, and drying the substrate, wherein the hydrophobic coating layer is formed using a coating agent that includes phosphate having more than one hydrocarbon group, phosphonate having more than one hydrocarbon group, or a mixture thereof.Type: ApplicationFiled: March 15, 2013Publication date: June 26, 2014Applicant: SK hynix Inc.Inventors: Sung-Hyuk CHO, Hyo-Sang KANG, Sung-Ki PARK, Kwon HONG, Hyung-Soon PARK, Hyung-Hwan KIM, Young-Bang LEE, Ji-Hye HAN, Tae-Yeon JUNG, Hyeong-Jin NOR
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Patent number: 8728887Abstract: A method for fabricating a capacitor of a semiconductor device includes sequentially forming an etch-stop layer and a mold layer over a substrate, sequentially forming a support layer and a hard mask pattern over the mold layer, forming a storage node hole by etching the support layer and the mold layer using the hard mask pattern as an etch barrier, forming a barrier layer on the sidewall of the mold layer inside the storage node hole, etching the etch-stop layer under the storage node hole, forming a storage node inside the storage node hole, and removing the hard mask pattern, the mold layer, and the barrier layer.Type: GrantFiled: May 10, 2012Date of Patent: May 20, 2014Assignee: Hynix SemiconductorInventors: Jeong-Yeop Lee, Hyung-Soon Park, Young-Bang Lee, Su-Young Kim
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Publication number: 20130164903Abstract: A method for fabricating a capacitor of a semiconductor device includes sequentially forming an etch-stop layer and a mold layer over a substrate, sequentially forming a support layer and a hard mask pattern over the mold layer, forming a storage node hole by etching the support layer and the mold layer using the hard mask pattern as an etch barrier, forming a barrier layer on the sidewall of the mold layer inside the storage node hole, etching the etch-stop layer under the storage node hole, forming a storage node inside the storage node hole, and removing the hard mask pattern, the mold layer, and the barrier layer.Type: ApplicationFiled: May 10, 2012Publication date: June 27, 2013Inventors: Jeong-Yeop Lee, Hyung-Soon Park, Young-Bang Lee, Su-Young Kim
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Patent number: 8187942Abstract: A method for manufacturing a semiconductor device having a dual gate insulation layer is presented. The method includes a step of forming a first insulation layer on a semiconductor substrate which has a first region and a second region. The method includes a step of selectively removing a portion of the first insulation layer formed the second region of the semiconductor substrate. The removal of the portion of the first insulation layer is conducted using an etching solution comprising propylene glycol, HF and amine. The method also includes a step of forming a second insulation layer on the first insulation layer in the first region and on the semiconductor substrate in the second region.Type: GrantFiled: December 10, 2009Date of Patent: May 29, 2012Assignee: Hynix Semiconductor Inc.Inventor: Young Bang Lee
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Patent number: 8007594Abstract: A method for manufacturing a semiconductor device includes the step of conducting a cleaning process for a wafer formed with copper wiring lines to remove contaminations produced on a back surface of the wafer. The cleaning process is conducted by injecting onto the back surface of the wafer an etchant for removing contaminations and simultaneously injecting onto a front surface of the wafer a reductant containing hydrogen.Type: GrantFiled: July 12, 2010Date of Patent: August 30, 2011Assignee: Hynix Semiconductor Inc.Inventors: Young Bang Lee, Kwang Kee Chae, Ok Min Moon
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Publication number: 20110159694Abstract: A method for fabricating a semiconductor device includes: providing a substrate, forming an insulation layer, an adhesive layer, and a photoresist pattern, etching the adhesive layer using the photoresist pattern as an etch barrier, and wet etching the insulation layer using the etched adhesive layer and the photoresist pattern as etch barriers.Type: ApplicationFiled: July 9, 2010Publication date: June 30, 2011Inventors: Young-Bang Lee, Ok-Min Moon
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Publication number: 20110155180Abstract: A wafer cleaning apparatus and a wafer cleaning method using the same are provided. The wafer cleaning method includes removing an oxide layer, which is formed on a wafer, by performing a dry cleaning process using hydrogen fluoride (HF) gas and ammonia (NH3) gas, and removing a reaction by-product generated during the dry cleaning process by performing a wet cleaning process which sprays a chemical onto the wafer.Type: ApplicationFiled: July 9, 2010Publication date: June 30, 2011Inventors: Ok-Min Moon, Young-Bang Lee
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Publication number: 20110023907Abstract: A method for manufacturing a semiconductor device includes the step of conducting a cleaning process for a wafer formed with copper wiring lines to remove contaminations produced on a back surface of the wafer. The cleaning process is conducted by injecting onto the back surface of the wafer an etchant for removing contaminations and simultaneously injecting onto a front surface of the wafer a reductant containing hydrogen.Type: ApplicationFiled: July 12, 2010Publication date: February 3, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Young Bang LEE, Kwang Kee CHAE, Ok Min MOON
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Patent number: 7855109Abstract: A method for manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a screen oxide layer over the surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed; forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto; removing the screen oxide film and simultaneously expanding the width of the second recess pattern; forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along the profile in the second recess pattern; forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess patter isType: GrantFiled: December 30, 2008Date of Patent: December 21, 2010Assignee: Hynix Semiconductor Inc.Inventors: Hyung Hwan Kim, Kwang Kee Chae, Jong Goo Jung, Ok Min Moon, Young Bang Lee, Sung Eun Park
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Publication number: 20100261325Abstract: A method for manufacturing a semiconductor device having a dual gate insulation layer is presented. The method includes a step of forming a first insulation layer on a semiconductor substrate which has a first region and a second region. The method includes a step of selectively removing a portion of the first insulation layer formed the second region of the semiconductor substrate. The removal of the portion of the first insulation layer is conducted using an etching solution comprising propylene glycol, HF and amine. The method also includes a step of forming a second insulation layer on the first insulation layer in the first region and on the semiconductor substrate in the second region.Type: ApplicationFiled: December 10, 2009Publication date: October 14, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Young Bang LEE
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Publication number: 20100151656Abstract: A method for manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a screen oxide layer over the surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed; forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto; removing the screen oxide film and simultaneously expanding the width of the second recess pattern; forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along the profile in the second recess pattern; forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess patter isType: ApplicationFiled: December 30, 2008Publication date: June 17, 2010Inventors: Hyung Hwan KIM, Kwang Kee CHAE, Jong Goo JUNG, Ok Min MOON, Young Bang LEE, Sung Eun PARK
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Publication number: 20090267199Abstract: An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer is formed in the trench including the first liner nitride layer. The flowable insulation layer is formed such to define a recess in the trench. A second liner nitride layer is formed on the recess including the flowable insulation layer and the first liner nitride layer. Finally, an insulation layer is formed in the recess on the second liner nitride layer to completely fill the trench.Type: ApplicationFiled: July 3, 2008Publication date: October 29, 2009Inventors: Hyung Hwan KIM, Kwang Kee CHAE, Jong Goo JUNG, Ok Min MOON, Young Bang LEE, Sung Eun PARK