Abstract: An embodiment solid electrolyte includes a first compound and a second compound. The first compound is represented by a first chemical formula Li7-aPS6-a(X11-bX2b)a, wherein X1 and X2 are the same or different and each represents F, Cl, Br, or I, and wherein 0<a?2 and 0<b<1, and the second compound is represented by a second chemical formula Li7-cP1-2dMdS6-c-3d(X11-eX2e)c, wherein X1 and X2 are the same or different and each represents F, Cl, Br, or I, wherein M represents Ge, Si, Sn, or any combination thereof, and wherein 0<c?2, 0<d<0.5, and 0<e<1.

Abstract: A device, apparatus and method for performing a Fast Fourier Transform (FFT). The Fast Fourier Transform (FFT) processing device includes a coefficient generator, a memory, and an accumulator. The coefficient generator is configured to generate a first set of coefficient values from one or more twiddle factor coefficients. The memory stores the first set of coefficient values. The accumulator receives and accumulates one or more coefficient values from the first set of coefficient values, the accumulator generating one or more output values based on the accumulated one or more coefficient values.

Abstract: A method for implementing a low power and high-speed digital filter having reduced number of adders is disclosed. The method comprises the steps of determining vertical common CSD (Canonical Signed Digit) code words between corresponding CSD code words of adjacent filter coefficients, wherein a vertical common CSD code word in a highest level bit is set as a vertical common subexpression, expressing the vertical common CSD code words out of the CSD code words of each filter coefficient with the vertical common subexpression by shifting and delaying the vertical common subexpression, and synthesizing the expressed vertical common CSD code words of the filter coefficients.

Abstract: A method for implementing a low power and high-speed digital filter having reduced number of adders is disclosed. The method comprises the steps of determining vertical common CSD (Canonical Signed Digit) code words between corresponding CSD code words of adjacent filter coefficients, wherein a vertical common CSD code word in a highest level bit is set as a vertical common subexpression, expressing the vertical common CSD code words out of the CSD code words of each filter coefficient with the vertical common subexpression by shifting and delaying the vertical common subexpression, and synthesizing the expressed vertical common CSD code words of the filter coefficients.

Abstract: An apparatus and method for digital filtering includes a method for implementing a digital filter having filter coefficients, each expressible as a canonical signed digit code word; where the method includes forming a virtual common subexpression that is relevant to a first filter coefficient, forming a second subexpression for a second filter coefficient in terms of the virtual common subexpression so that adders are shared with the virtual common subexpression in a tap line of the second filter coefficients; and the resulting digital filter receives digital samples of input signals, shifts the received digital samples by bit-shift values of filter coefficients that are defined relative to the virtual common subexpression, adds shifted digital samples to drive a common tap line, adds shifted digital samples to the output of the common tap line to drive a tap line corresponding to a filter coefficient, and delays an output signal component corresponding to a tap line.