Abstract: A semiconductor device including an insulating capping structure is provided. The semiconductor device may include a plurality of gate electrodes vertically stacked on a substrate and an insulating capping structure on the plurality of gate electrodes. The insulating capping structure may include a first upper surface and a second upper surface. A first distance between the first upper surface and the substrate may be greater than a second distance between the second upper surface and the substrate. The first upper surface may not overly the second upper surface. The semiconductor device may include a memory cell vertical structure passing through the first upper surface, the plurality of gate electrodes, and the insulating capping structure. The memory cell vertical structure may be spaced apart from the second upper surface. The semiconductor device may include a bit line electrically connected to the memory cell vertical structure.

Abstract: A semiconductor device including an insulating capping structure is provided. The semiconductor device may include a plurality of gate electrodes vertically stacked on a substrate and an insulating capping structure on the plurality of gate electrodes. The insulating capping structure may include a first upper surface and a second upper surface. A first distance between the first upper surface and the substrate may be greater than a second distance between the second upper surface and the substrate. The first upper surface may not overly the second upper surface. The semiconductor device may include a memory cell vertical structure passing through the first upper surface, the plurality of gate electrodes, and the insulating capping structure. The memory cell vertical structure may be spaced apart from the second upper surface. The semiconductor device may include a bit line electrically connected to the memory cell vertical structure.

Abstract: According to example embodiments of inventive concepts, a non-volatile memory device includes a substrate including a second impurity region crossing a first impurity region, and channel regions extending in a vertical direction on the substrate. Gate electrodes may be separated from each other in a vertical direction and a horizontal direction along outer walls of the channel regions. A first insulating interlayer may be on the gate electrodes and the channel regions, where the first insulating interlayer defines a contact hole between at least one adjacent pair gate electrodes and a contact plug is formed in the contact hole to be electrically connected to the second impurity region. An etch stop layer pattern may be on the contact plug and the first insulating interlayer.

Abstract: According to example embodiments of inventive concepts, a non-volatile memory device includes a substrate including a second impurity region crossing a first impurity region, and channel regions extending in a vertical direction on the substrate. Gate electrodes may be separated from each other in a vertical direction and a horizontal direction along outer walls of the channel regions. A first insulating interlayer may be on the gate electrodes and the channel regions, where the first insulating interlayer defines a contact hole between at least one adjacent pair gate electrodes and a contact plug is formed in the contact hole to be electrically connected to the second impurity region. An etch stop layer pattern may be on the contact plug and the first insulating interlayer.