Abstract: A flash memory device can include a bank including normal memory cells and redundant memory cells arranged in a matrix of rows and columns. A read redundancy circuit is configured to generate read repair information in response to read address information during a read operation. A write redundancy circuit is configured to generate write repair information in response to write address information during a write operation. A write driver circuit is configured to drive normal and/or redundant memory cells with data bits to be written in response to the write repair information. A sense amplifier circuit is configured to sense and amplify data bits from normal memory cells and a data bit from a redundant memory cell in the bank and to replace one of the sensed data bits from the normal memory cells with the sensed data bit read from the redundant memory cell in response to the read repair information.