Patents by Inventor Young-Chai Jung

Young-Chai Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10790368
    Abstract: VFET devices are provided. A VFET device includes a substrate including first and second protruding portions. The VFET device includes an isolation region between the first and second protruding portions. The VFET device includes first and second silicide regions on the first and second protruding portions, respectively. Moreover, the VFET device includes a contact on the first and second silicide regions. Related methods of forming a VFET device are also provided.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: September 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Chai Jung, Myung Gil Kang, Kang Ill Seo, Seon Bae Kim, Yong Hee Park
  • Patent number: 10724967
    Abstract: An inspection apparatus for a semiconductor process and a semiconductor process device, the inspection apparatus including a transferer configured to transfer a process object between a plurality of chambers; at least one line camera installed above the transferer, the at least one line camera being configured to generate an original image by capturing an image of the process object transferred by the transferer; and a controller configured to receive the original image and to perform an inspection of the process object by correcting distortion of the original image due to a change in transfer speed of the transferer.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myung Ho Jung, Young Su Ryu, Sung Chai Kim, Jong Su Kim, Won Guk Seo, Chang Hoon Choi, Jeong Su Ha
  • Publication number: 20200144254
    Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a channel region protruding from a substrate in a vertical direction, a first source/drain region, and a second source/drain region. The first source/drain region may vertically overlap the channel region. The first and second source/drain regions may contact a first portion and a second portion of the channel region, respectively, and a third portion of the channel region between the first and second portions may include a first channel region extending longitudinally in a first horizontal direction that is perpendicular to the vertical direction and a second channel region extending longitudinally in a second horizontal direction that is perpendicular to the vertical direction and traverses the first horizontal direction. The integrated circuit devices may also include a gate structure on opposing vertical sides of the channel region.
    Type: Application
    Filed: March 19, 2019
    Publication date: May 7, 2020
    Inventors: Seung Hyun SONG, Young Chai JUNG
  • Publication number: 20190355822
    Abstract: VFET devices are provided. A VFET device includes a substrate including first and second protruding portions. The VFET device includes an isolation region between the first and second protruding portions. The VFET device includes first and second silicide regions on the first and second protruding portions, respectively. Moreover, the VFET device includes a contact on the first and second silicide regions. Related methods of forming a VFET device are also provided.
    Type: Application
    Filed: February 14, 2019
    Publication date: November 21, 2019
    Inventors: YOUNG CHAI JUNG, MYUNG GIL KANG, KANG ILL SEO, SEON BAE KIM, YONG HEE PARK
  • Publication number: 20190323973
    Abstract: An inspection apparatus for a semiconductor process and a semiconductor process device, the inspection apparatus including a transferer configured to transfer a process object between a plurality of chambers; at least one line camera installed above the transferer, the at least one line camera being configured to generate an original image by capturing an image of the process object transferred by the transferer; and a controller configured to receive the original image and to perform an inspection of the process object by correcting distortion of the original image due to a change in transfer speed of the transferer.
    Type: Application
    Filed: January 8, 2019
    Publication date: October 24, 2019
    Inventors: Myung Ho JUNG, Young Su RYU, Sung Chai KIM, Jong Su KIM, Won Guk SEO, Chang Hoon CHOI, Jeong Su HA
  • Patent number: 9490177
    Abstract: An integrated circuit can include first and second FETs of a particular conductivity type on a substrate, wherein a first source/drain region of the first FET is closer to a center of a first channel region of the first FET than a second source/drain region of the second FET is to a center of a second channel region of the second FET.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Oh, Myung-Gil Kang, Young-Chai Jung
  • Publication number: 20130285143
    Abstract: An integrated circuit can include first and second FETs of a particular conductivity type on a substrate, wherein a first source/drain region of the first FET is closer to a center of a first channel region of the first FET than a second source/drain region of the second FET is to a center of a second channel region of the second FET.
    Type: Application
    Filed: September 14, 2012
    Publication date: October 31, 2013
    Inventors: Chang-Woo Oh, Myung-Gil Kang, Young-Chai Jung