Patents by Inventor Young Chang

Young Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961775
    Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: April 16, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
  • Publication number: 20240119064
    Abstract: Disclosed herein is an apparatus and method for synchronizing a block in a blockchain network. The apparatus synchronizes node information of existing participating nodes connected to a blockchain network by joining the blockchain network, determines synchronization target blocks by calculating the current section of a blockchain using an agreed-upon block received from the existing participating nodes, receives a block header of each section and the segment hash table of a snapshot that are verification data for verifying synchronization target data for the synchronization target blocks from participating nodes that are not connected as peers, among the existing participating nodes, generates a snapshot by receiving snapshot segments and the blocks of the current section, which are the synchronization target data, from participating nodes connected as peers, among the existing participating nodes, verifies the snapshot generated from the snapshot segments, and synchronizes the verified snapshot.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 11, 2024
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young-Chang KIM, Jong-Choul YIM, Jin-Tae OH, Chang-Hyun LEE
  • Publication number: 20240121122
    Abstract: Disclosed are an apparatus and method for electing a committee node in a blockchain. The apparatus for electing a committee node in a blockchain is configured to transmit a staking transaction including validator information to a blockchain system to register a validator node, generate a draw pool for electing a committee node based on the validator information, change entries of the draw pool using a predefined shuffling algorithm, select a preset number of top entries as votes of a committee member from among the entries of the shuffled draw pool, and elect, as the committee node, the validator node that has acquired votes of a committee.
    Type: Application
    Filed: August 23, 2023
    Publication date: April 11, 2024
    Inventors: Jong-Choul YIM, Jin-Tae OH, Young-Chang KIM, Chang-Hyun LEE
  • Patent number: 11955076
    Abstract: An example method includes estimating, based on content to be displayed at a display of a mobile computing device at a future time, an amount of power to be used by the display at the future time; selecting, based on the estimated power level, a power converter of a plurality of power converters of the mobile computing device, each of the plurality of power converters optimized for a different output power range; and causing electrical power from the selected power converter to be supplied to the display at the future time.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: April 9, 2024
    Assignee: Google LLC
    Inventors: Ji Hoon Lee, Sun-il Chang, Sang Young Youn
  • Patent number: 11954891
    Abstract: Provided is a method of compressing an occupancy map of a three-dimensional (3D) point cloud, and more specifically, a method of compressing an occupancy map of a point cloud in which an occupancy map image of a point cloud existing in a 3D space is compressed based on a compression quality or a patch-by-patch inspection method of the occupancy map image so that compression distortion is minimized when reconstructing the compressed occupancy map image so as to remarkably improve the quality of a reconstructed occupancy map image.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: April 9, 2024
    Assignees: Electronics and Telecommunications Research Institute, IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)
    Inventors: Eun Young Chang, Euee Seon Jang, Tian Yu Dong, Ji Hun Cha, Kyu Tae Kim, Jae Young Ahn
  • Publication number: 20240111785
    Abstract: Disclosed herein is a method for adding an additional chain to a blockchain. The method includes depositing, by a node of the blockchain, an asset corresponding to the additional chain; selecting the node as one of consensus nodes for connecting an additional block to the additional chain based on a share value corresponding to the asset; and performing, by the node, distributed consensus for connecting the additional block. Here, nodes constituting the blockchain include major shareholder nodes for processing transactions.
    Type: Application
    Filed: April 10, 2023
    Publication date: April 4, 2024
    Inventors: Jin-Tae OH, Young-Chang KIM, Chang-Hyun LEE, Jong-Choul YIM
  • Publication number: 20240114163
    Abstract: Disclosed is an encoder which receives first to third input frames included first intra period and outputs a bitstream corresponding to the third input frame. The encoder includes a motion compensation unit that generates a first reference frame corresponding to the first input frame and a second reference frame corresponding to the second input frame, a union operation unit that generates an overlap frame by performing a union operation based on the first reference frame and the second reference frame, and an inter prediction unit that generates an occupancy code by performing an inter prediction operation on the overlap frame and the third input frame. In this case, the bitstream includes the occupancy code.
    Type: Application
    Filed: September 15, 2023
    Publication date: April 4, 2024
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Eun Young CHANG, Euee S JANG, Xin LI, Jihun CHA, Tianyu DONG, Jae Young AHN
  • Patent number: 11946607
    Abstract: A lighting device disclosed in an embodiment of the invention includes a substrate; light sources disposed on the substrate; and a resin layer disposed on the substrate and the light sources. a first reflective layer disposed on the resin layer, wherein the resin layer includes an exit surface facing the light sources, and the exit surface of the resin layer includes convex portions facing each of the light sources and recess portions respectively disposed between the plurality of convex portions, concave surfaces disposed in each of the plurality of recess portions may have a curvature, and a radius of curvature of the concave surfaces may increase in one direction.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: April 2, 2024
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Young Jae Choi, Dong Hyun Lee, Ki Chang Lee, Gyeong Il Jin, Moo Ryong Park
  • Patent number: 11948520
    Abstract: PWM-frame rate misalignment is mitigated through implementation of a discrete variable refresh rate (VRR) scheme. A target frame rate is limited to a frame rate selected from only those frame rates that facilitate alignment of each frame period to a specified edge of a PWM cycle of a brightness control signal of a display panel. This alignment results in each frame period at the selected frame rate starting at a same point in a corresponding PWM cycle and ending at a same point in a corresponding PWM cycle to help ensure a constant effective duty cycle across each successive frame period, which in turn mitigates perception of flicker that otherwise would arise. Further, the discrete VRR scheme can employ a compensation mode for compensating for the delay in rendering or otherwise obtaining a frame for display so as to maintain a consistent duty cycle in the brightness control signal.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: April 2, 2024
    Assignee: GOOGLE LLC
    Inventors: Sang Young Youn, Sun-il Chang, Wonjae Choi, Sangmoo Choi
  • Patent number: 11948614
    Abstract: The present disclosure relates to methods of manufacturing at least a portion of a magnetic layer of a magnetic recording disk. The methods include forming a plurality of sacrificial, discrete structures via imprint lithography. The sacrificial, discrete structures are used to form a plurality of three-dimensional segregant structures in a magnetic layer of the magnetic recording disk. The present disclosure also relates to corresponding magnetic recording disks.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: April 2, 2024
    Assignee: Seagate Technology LLC
    Inventors: Xiaomin Yang, Kim Yang Lee, Thomas Young Chang, ShuaiGang Xiao, Sha Zhu
  • Publication number: 20240106421
    Abstract: In an embodiment, an apparatus is disclosed that includes a duty cycle controller. The duty cycle controller includes a tuning circuit comprising a first field-effect transistor. The first field-effect transistor is configured to implement a capacitor. The duty cycle controller further includes an edge delay circuit. The edge delay circuit includes a second field-effect transistor that, when activated by an input clock signal of the duty cycle controller, is configured to connect a voltage source to an output clock signal of the duty cycle controller. The edge delay circuit further includes a third field-effect transistor that, when activated, is configured to connect the first field-effect transistor of the tuning circuit to the output clock signal.
    Type: Application
    Filed: December 6, 2023
    Publication date: March 28, 2024
    Applicant: Renesas Electronics America Inc.
    Inventors: Dong-Young CHANG, Steven Ernest FINN
  • Publication number: 20240097770
    Abstract: An operation method of a first access point (AP) may comprise: transmitting, to a control device of a base station, channel information between the first AP and one or more user equipments (UEs) connected to the base station; receiving allocation information determined by the control device; identifying an entity to decode a uplink (UL) signal of each of the one or more UEs from among a plurality of APs and the control device constituting the base station, based on the allocation information; directly performing a decoding operation on a first UL signal received from a first UE among the one or more UEs, based on the allocation information; and transmitting, to the control device, a first report related to a result of the decoding operation on the first UL signal.
    Type: Application
    Filed: December 29, 2022
    Publication date: March 21, 2024
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Jung Ho MYUNG, Young-Jo KO, Keun Young KIM, Kapseok CHANG
  • Patent number: 11935808
    Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Je-Young Chang, Ram Viswanath, Elah Bozorg-Grayeli, Ahmad Al Mohammad
  • Publication number: 20240083850
    Abstract: The present invention pertains to a novel lappaconitine derivative, a method for producing same, and a pharmaceutical use thereof using osteogenesis-promoting activity. The lappaconitine derivative induces the differentiation of stem cells into osteoblasts, increases bone mineral density when administered to animal models of osteoporosis, and induces bone formation in animal models of bone fracture, and thus can be advantageously used for preventing, ameliorating, or treating bone-related diseases such as osteoporosis, as well as treating non-disease fractures caused by physical trauma.
    Type: Application
    Filed: March 5, 2021
    Publication date: March 14, 2024
    Applicant: QGENETICS CO., LTD.
    Inventors: Mun Seog CHANG, Tae Hee LEE, Ha Young KIM, Jung Bin MIN
  • Publication number: 20240083851
    Abstract: The present invention relates to a novel lappaconitine derivative and a pharmaceutically acceptable salt thereof, a preparation method therefor, and a medical use thereof using osteogenesis-promoting activity. The lappaconitine derivative induces the differentiation of stem cells into preosteoblasts, and increases bone density when administered to an osteoporosis animal model, and induces osteogenesis, and thus can be effectively used for preventing, alleviating, or treating bone-related diseases such as osteoporosis.
    Type: Application
    Filed: March 5, 2021
    Publication date: March 14, 2024
    Applicant: QGENETICS CO., LTD.
    Inventors: Mun Seog CHANG, Tae Hee LEE, Ha Young KIM, Jung Bin MIN
  • Patent number: 11929018
    Abstract: A frame generation subsystem renders a sequence of frames and a display control subsystem provides a brightness control signal configured to control a brightness of frames displayed at a display panel via pulse width modulation (PWM) of the brightness control signal and determines a deviation in a duty cycle of a first PWM period of the brightness control signal from a default duty cycle resulting from a delayed rendering of a frame. The display control subsystem adjusts a duty cycle of at least a second PWM period to compensate for the deviation in the duty cycle of the first PWM period. The resulting average duty cycle of the brightness control signal over the two frame periods is approximately equal to a default duty cycle and thereby mitigates viewable flicker resulting from the duty cycle change caused by the delayed rendering.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: March 12, 2024
    Assignee: GOOGLE LLC
    Inventors: Sang Young Youn, Sun-il Chang, Wonjae Choi, Hyunchul Kim
  • Publication number: 20240080826
    Abstract: A method may comprise: generating first and second FA sequences corresponding to first and second FAs, respectively, based on a first sequence; mapping elements of first and second FA signals, which are respectively generated by modulating the first and second FA sequences, to first and second subcarrier groups corresponding to the first and second FAs, first base station, and first symbol; generating third and fourth FA sequences corresponding to the first and second FAs, respectively, based on a second sequence; mapping elements of third and fourth FA signals, which are respectively generated by modulating the first and second FA sequences, to third and fourth subcarrier groups corresponding to the first and second FAs, second base station, and second symbol; and transmitting a first transmission signal including the first and second FA signals, and a second transmission signal including the third and fourth FA signals.
    Type: Application
    Filed: June 20, 2023
    Publication date: March 7, 2024
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kapseok CHANG, Cheul Soon KIM, Young-Jo KO, Jung Hoon LEE
  • Patent number: 11918848
    Abstract: Proposed is a slat having a truss structure, the slat including: a main body provided with a stepping part which receives the load of a user, and a coupling part which is formed on both sides of the stepping part and may be fixed to a track belt; and a truss part connected to the stepping part so as to distribute the load applied to the main body. Thus, since the load applied to the stepping part is distributed by a diagonal member part and a chord member part of the truss part, the bending of the main body caused by the load is minimized, and thus damage to the main body caused by the load may be prevented.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: March 5, 2024
    Inventors: Bo Young Chang, Min Wung Kim
  • Patent number: 11923267
    Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Je-Young Chang, Ram Viswanath, Elah Bozorg-Grayeli, Ahmad Al Mohammad
  • Publication number: 20240074296
    Abstract: A display panel includes a first substrate including a display area, in which a plurality of pixel areas is arranged, and a non-display area around the display area, a second substrate disposed opposite to the first substrate, a light emitting array disposed on the first substrate and including a plurality of light emitting elements corresponding to the plurality of pixel areas, a sealing layer disposed in the non-display area between the first substrate and the second substrate and bonding the first substrate and the second substrate to each other, a vacuum layer sealed by the sealing layer and defined between the light emitting array and the second substrate, and a reflection adjustment layer disposed on the second substrate and absorbing a portion of external light, where the reflection adjustment layer includes a plurality of protrusions protruding toward the light emitting array and exposed to the vacuum layer.
    Type: Application
    Filed: April 12, 2023
    Publication date: February 29, 2024
    Inventors: Jong Ho SON, Dae Won KIM, Hye Beom SHIN, Jin Hyeong LEE, Sun Young CHANG