Patents by Inventor Young-Cheon Kim

Young-Cheon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230001377
    Abstract: The present invention relates to a hydrogen production reactor comprising a high-efficiency composite having a high thermal conductivity and an antioxidant property. Specifically, the hydrogen production reactor comprises: a first region in which a combustion reaction of fuel occurs; a second region in which a hydrogen extraction reaction occurs; a metal substrate that partitions the first region and the second region; and a coating layer that comprises boron nitride (BN) and is formed on at least one surface of the metal substrate, wherein heat generated in the first region is transferred to the second region through the metal substrate.
    Type: Application
    Filed: August 29, 2022
    Publication date: January 5, 2023
    Inventors: Young Suk JO, Arash BADAKHSH, Jun Young CHA, Young Cheon KIM, Hyang Soo JEONG, Yong Min KIM, Hyun Tae SOHN, Seong Cheol JANG, Sung Pil YOON, Suk Woo NAM, Taik Jin LEE, Chang Won YOON, Jong Hee HAN
  • Patent number: 10281379
    Abstract: A nano material testing apparatus includes a main frame; a testing unit including an actuator and a load cell connected to the actuator; a jig unit configured to be connected to the testing unit and including an upper jig that clamps one side of an upper portion of the nano material specimen and a lower jig that is located below the upper jig and clamps one side of a lower portion of the nano material specimen; a stage unit configured to be connected to the lower jig; a first alignment unit configured to be located to be spaced apart from a front surface of the nano material specimen; a second alignment unit configured to be located to be spaced apart from side surfaces of the nano material specimen; and a controller.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: May 7, 2019
    Assignee: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
    Inventors: Ju Young Kim, Young Cheon Kim, Si Hoon Kim
  • Publication number: 20170363523
    Abstract: A nano material testing apparatus includes a main frame; a testing unit including an actuator and a load cell connected to the actuator; a jig unit configured to be connected to the testing unit and including an upper jig that clamps one side of an upper portion of the nano material specimen and a lower jig that is located below the upper jig and clamps one side of a lower portion of the nano material specimen; a stage unit configured to be connected to the lower jig; a first alignment unit configured to be located to be spaced apart from a front surface of the nano material specimen; a second alignment unit configured to be located to be spaced apart from side surfaces of the nano material specimen; and a controller.
    Type: Application
    Filed: December 7, 2016
    Publication date: December 21, 2017
    Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
    Inventors: Ju Young KIM, Young Cheon KIM, Si Hoon KIM
  • Patent number: 7504725
    Abstract: A semiconductor memory device and a method of manufacturing the semiconductor memory device, in which a bit line can have a low resistance without an increase in the thickness of the bit line. In the semiconductor memory device, an insulating layer having a contact hole that exposes a conductive region is formed on a semiconductor substrate having the conductive region. A barrier metal layer is formed along the surface of the insulating layer and the surface of the contact hole. A grain control layer is formed between the barrier metal layer and the tungsten layer. A tungsten layer is formed on the grain control layer. A grain size of the tungsten layer is increased by the grain control layer.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: March 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Rak-Hwan Kim, Young-Cheon Kim, Hyeon-Deok Lee, Hyun-Young Kim, In-Sun Park
  • Publication number: 20070026671
    Abstract: Provided is a method for forming low resistance metal films in which an underlying film, for example, a barrier layer or an adhesion layer, is formed on a semiconductor substrate. The underlying film is then subjected to a partial etch back in order to reduce the surface roughness and form a deposition surface. A metal film, for example, a tungsten film, is then formed on a deposition surface that has been formed on the underlying film. Forming the metal film on the deposition surface that has reduced surface roughness will tend to produce a metal film having a larger average grain size and, consequently, a lower sheet resistivity for a given film thickness.
    Type: Application
    Filed: June 29, 2006
    Publication date: February 1, 2007
    Inventors: Rak-Hwan Kim, Young-Cheon Kim
  • Publication number: 20060281289
    Abstract: In a method of forming a polycide layer and method of manufacturing a semiconductor device having the polycide layer, the method may include forming a preliminary polysilicon layer doped with first type impurities on a substrate having a first region and a second region, implanting second type of impurities into a portion of the preliminary polysilicon layer on the second region, heat treating the preliminary polysilicon layer to electrically activate the impurities, removing a portion of an upper surface of the heat treated preliminary polysilicon layer to obtain a polysilicon layer, forming a metal silicide layer on the polysilicon layer, and patterning the polysilicon layer and the metal silicide layer to form a first type gate electrode on the first region and to form a second type gate electrode on the second region.
    Type: Application
    Filed: June 6, 2006
    Publication date: December 14, 2006
    Inventors: Young-Cheon Kim, Chul Hwangbo, Rak-Hwan Kim, Hyeon-Deok Lee, In-Sun Park, Ji-Soon Park
  • Publication number: 20050042829
    Abstract: A semiconductor memory device and a method of manufacturing the semiconductor memory device, in which a bit line can have a low resistance without an increase in the thickness of the bit line. In the semiconductor memory device, an insulating layer having a contact hole that exposes a conductive region is formed on a semiconductor substrate having the conductive region. A barrier metal layer is formed along the surface of the insulating layer and the surface of the contact hole. A grain control layer is formed between the barrier metal layer and the tungsten layer. A tungsten layer is formed on the grain control layer. A grain size of the tungsten layer is increased by the grain control layer.
    Type: Application
    Filed: August 9, 2004
    Publication date: February 24, 2005
    Inventors: Rak-Hwan Kim, Young-Cheon Kim, Hyeon-Deok Lee, Hyun-Young Kim, In-Sun Park
  • Patent number: 6797575
    Abstract: A method for preventing void formation in a polycide structure includes sequentially depositing a gate oxide film, a polysilicon film doped with impurities, a seed film having a sufficient amount of silicon for reacting with an overlaying tungsten layer, a tungsten silicide precursor layer; and an etch mask made of an insulating material on a semiconductor substrate; performing a patterned etching using the etch mask; and heat-treating the resulting structure in an oxygen atmosphere at an elevated temperature and pressure to form a polycide structure wherein void formation is prevented. Since the seed film has a sufficient amount of amorphous silicon for reacting to the tungsten, migration of silicon atoms to the interfacial surface between the polysilicon film and the tungsten silicide precursor layer is prevented, thereby preventing the formation of voids in the polysilicon film.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: September 28, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Cheon Kim, In-Sun Park, Ju-Cheol Shin
  • Publication number: 20030219536
    Abstract: A chemical vapor deposition (CVD) method for depositing a silicide and a CVD system for performing the same are disclosed. A silicide is deposited on a substrate. Residual gases remaining from the depositing step are purged out by flowing air including H2O (g), to substantially remove fumes caused by the residual gases. In the purge step, the cycle purge is carried out at the conditions similar to the flow of atmosphere, to substantially remove the fumes.
    Type: Application
    Filed: June 24, 2003
    Publication date: November 27, 2003
    Inventors: Ju-Cheol Shin, In-Sun Park, Young-Cheon Kim, Chul Whang-Bo, Hyeon-Deok Lee
  • Patent number: 6623798
    Abstract: A chemical vapor deposition (CVD) method for depositing a suicide and a CVD system for performing the same are disclosed. A silicide is deposited on a substrate. Residual gases remaining from the depositing step are purged out by flowing air including H2O (g), to substantially remove fumes caused by the residual gases. In the purge step, the cycle purge is carried out at the conditions similar to the flow of atmosphere, to substantially remove the fumes.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: September 23, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Cheol Shin, In-Sun Park, Young-Cheon Kim, Chul Whang-Bo, Hyeon-Deok Lee
  • Publication number: 20020197859
    Abstract: A method for preventing void formation in a polycide structure includes sequentially depositing a gate oxide film, a polysilicon film doped with impurities, a seed film having a sufficient amount of silicon for reacting with an overlaying tungsten layer, a tungsten silicide precursor layer; and an etch mask made of an insulating material on a semiconductor substrate; performing a patterned etching using the etch mask; and heat-treating the resulting structure in an oxygen atmosphere at an elevated temperature and pressure to form a polycide structure wherein void formation is prevented. Since the seed film has a sufficient amount of amorphous silicon for reacting to the tungsten, migration of silicon atoms to the interfacial surface between the polysilicon film and the tungsten silicide precursor layer is prevented, thereby preventing the formation of voids in the polysilicon film.
    Type: Application
    Filed: March 20, 2002
    Publication date: December 26, 2002
    Inventors: Young-Cheon Kim, In-Sun Park, Ju-Cheol Shin
  • Patent number: 6451691
    Abstract: A method of manufacturing a metal pattern of a semiconductor device. A Ti layer and a metal layer are successively formed on a semiconductor substrate or on an insulating layer. Then, a wiring pattern including a Ti layer pattern and a metal layer pattern is formed by patterning said Ti layer and the metal layer. Heat treating is employed under an atmosphere of a compound including nitrogen in order to react an exposed portion of the Ti layer pattern to form TiN as a main product, thereby increasing the stability and adhesiveness of the metal layer for subsequent processes.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: September 17, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Sang Song, In-Sun Park, Kyung-Bum Koo, Young-Cheon Kim
  • Publication number: 20020014205
    Abstract: A chemical vapor deposition (CVD) method for depositing a suicide and a CVD system for performing the same are disclosed. A silicide is deposited on a substrate. Residual gases remaining from the depositing step are purged out by flowing air including H2O (g), to substantially remove fumes caused by the residual gases. In the purge step, the cycle purge is carried out at the conditions similar to the flow of atmosphere, to substantially remove the fumes.
    Type: Application
    Filed: June 21, 2001
    Publication date: February 7, 2002
    Inventors: Ju-Cheol Shin, In-Sun Park, Young-Cheon Kim, Chul Whang-Bo, Hyeon-Deok Lee
  • Publication number: 20020001945
    Abstract: A method of manufacturing a metal pattern of a semiconductor device. A Ti layer and a metal layer are successively formed on a semiconductor substrate or on an insulating layer. Then, a wiring pattern including a Ti layer pattern and a metal layer pattern is formed by patterning said Ti layer and the metal layer. Heat treating is employed under an atmosphere of a compound including nitrogen in order to react an exposed portion of the Ti layer pattern to form TiN as a main product, thereby increasing the stability and adhesiveness of the metal layer for subsequent processes.
    Type: Application
    Filed: February 28, 2001
    Publication date: January 3, 2002
    Inventors: Won-Sang Song, In-Sun Park, Kyung-Bum Koo, Young-Cheon Kim
  • Patent number: D463616
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: September 24, 2002
    Assignee: Colibri Corporation
    Inventor: Young Cheon Kim
  • Patent number: D463882
    Type: Grant
    Filed: January 4, 2002
    Date of Patent: October 1, 2002
    Assignee: Colibri Corporation
    Inventor: Young Cheon Kim