Abstract: Provided is a multi-port cache memory apparatus and a method of the multi-port cache memory apparatus. The multi-port memory apparatus may divide an address space into address regions and allocate the divided memory regions to cache banks, thereby preventing the concentration of access to a particular cache.

Abstract: A semiconductor memory device has a clock input buffer that is turned ‘on’ or ‘off’ in response to a first control signal. The clock input buffer is configured to buffer an external clock signal in order to output a buffered clock signal. The memory device further includes an internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal. The generation of the internal clock signal is started in response to a second control signal.

Abstract: A multiprocessor using a shared virtual memory (SVM) is provided. The multiprocessor includes a plurality of processing cores and a memory manager configured to transform a virtual address into a physical address to allow a processing core to access a memory region corresponding to the physical address.

Abstract: An output driving circuit includes a first pull-up transistor, a first pull-down transistor and a second pull-down transistor. The first pull-up transistor is configured to generate a first output signal at the output node in response to a first control signal. The first pull-down transistor is configured to generate a second output signal at the output node in response to a second control signal. The second pull-down transistor is configured to connect the output node to the first ground voltage in response to a third control signal. The memory device including the output driving circuit may be insensitive to noise and may have little data transmission error.

Abstract: A simulation apparatus and method for a multicore system are provided. The simulation apparatus may prevent the occurrence of a data collision during the communication between modules and may reduce the overhead generated during simulation. The simulation apparatus may select a plurality of modules to be synchronized in terms of function execution timing based on timing information and may configure a multicore system architecture model using the selected modules. The simulation apparatus may acquire function execution timing information of the modules, control the execution of functions by the modules based on the acquired function execution timing information, and output the results of the control of the execution of functions by the modules.

Abstract: A three-dimensional (3D) display device for providing an input-output interface using a dynamic magnetic field control is disclosed, the device including a display unit to display a 3D image, a magnetic field generation unit to generate a magnetic field, and a control unit to dynamically control the magnetic field generation unit to generate a 3D magnetic field associated with the 3D image.

Abstract: An interactive method includes displaying image content received through a television (TV) network, identifying an object of interest of a user among a plurality of regions or a plurality of objects included in the image content, and providing additional information corresponding to the object of interest.

Abstract: A routing apparatus and a network apparatus that are capable of improving general system performance by compressing/decompressing data and transmitting the result of the compression/decompression, are provided. The routing apparatus may compress and/or decompress input data, and may transmit the compressed and/or decompressed input data.

Abstract: Provided are a simulator of a multi-core system employing reconfigurable processor (RP) cores and a method of simulating a multi-core system employing RP cores. The simulator includes a structure builder to receive a structure definition file defining a structure of a system, select components described in the structure definition file from a component library, and fill a data structure with the selected components to generate a structure model of a multi-core system, and a simulation engine to execute an application program according to the structure model and output the result.

Abstract: A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.

Abstract: A processor simulation technique to evaluate the performance of a processor that executes application programs is provided. The processor simulation technique may be used to optimize the execution of an application program. A simulator of a reconfigurable processor including a plurality of functional units models a processor by representing routing paths between functional units that generate operands and functional units that consume the operands. The size of each queue may be decided based on information regarding routing delays between functional units and stage information of iteration loops according to modulo scheduling received from a scheduler. A modeling code DB that stores host-oriented binary codes for operations of routing queues is also provided. The simulation may be performed by executing a host-directed binary code corresponding to a binary file instead of the binary file.

Abstract: A computing apparatus for accessing a multiple bank memory is provided. The computing apparatus includes a processor, a memory and a memory controller which is configured to store data in a data buffer by accessing the memory in an aligned word unit and output, in response to a request for an unaligned memory access by the processor, requested data by extracting the request data from the data buffer.

Abstract: Exemplary embodiments disclose a method for generating an assertion based on a user program code. The method may include receiving a user program comprising at least one assertion directive, a compiled result of the user program, and architecture information of a processor, and generating, based on the compiled result of the user program and the architecture information of the processor, an assertion which states an operation that the processor needs to perform in accordance with a code of the user program indicated by each of the at least one assertion directive.

Abstract: Provided are a source level debugging apparatus and method for a coarse grained array (CGA)-based reconfigurable processor. The source level debugging apparatus may determine valid operations for setting a breakpoint in a result of source code scheduling using invalid operation information, and may set the breakpoint at an address corresponding to the determined valid operations.

Abstract: An input receiver circuit including a single-to-differential amplifier and a semiconductor device including the input receiver circuit are disclosed. The input receiver circuit includes a first stage amplifier unit and a second stage amplifier unit. The first stage amplifier unit amplifies a single input signal in a single-to-differential mode to generate a differential output signal, without using a reference voltage. The second stage amplifier unit amplifies the differential output signal in a differential-to-single mode to generate a single output signal.

Abstract: A semiconductor memory device and a power line arrangement method are disclosed. The semiconductor memory device includes a plurality of pads, each pad including an upper pad and a lower pad arranged below the upper pad, wherein pad power lines are arranged below the lower pads of the plurality of pads in a direction of crossing the pads to interconnect the pads that transmit the same level of electrical power among the plurality of pads.

Abstract: A verification supporting apparatus and a verification supporting method of a reconfigurable processor is provided. The verification supporting apparatus includes an invalid operation determiner configured to detect an invalid operation from a result of scheduling on a source code, and a masking hint generator configured to generate a masking hint for the detected invalid operation.

Abstract: An output driving circuit includes a first pull-up transistor, a first pull-down transistor and a second pull-down transistor. The first pull-up transistor is configured to generate a first output signal at the output node in response to a first control signal. The first pull-down transistor is configured to generate a second output signal at the output node in response to a second control signal. The second pull-down transistor is configured to connect the output node to the first ground voltage in response to a third control signal. The memory device including the output driving circuit may be insensitive to noise and may have little data transmission error.

Abstract: A power mixing circuit capable of maintaining a stable output voltage in a deep-power- down mode is provided. The power mixing circuit includes an input buffer, a power mixing control circuit, a power mixing driver and an output buffer. The input buffer is configured to operate using a first supply voltage, and to generate a first voltage signal in response to an input signal. The power mixing control circuit is configured to generate a power mixing control signal based on a power-up signal and a deep-power-down mode signal. The power mixing driver is configured to operate using an external supply voltage and a second supply voltage, to perform power mixing on the external supply voltage and the second supply voltage, and to generate a second voltage signal. The output buffer is configured to operate using the second supply voltage, and to generate an output signal.

Abstract: Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.