Abstract: A multilayer ceramic capacitor includes first through fourth internal electrodes. The first and second internal electrodes are connected to first and second external electrodes, respectively, and disposed to face each other. The third and fourth internal electrodes are connected to the first and second external electrodes, respectively, and disposed to face each other, with a connection area of the third and fourth internal electrodes with the first and second external electrodes being different from the connection area where the first and second internal electrodes connect with the first and second external electrodes. The first and second external electrodes include first and second conductive layers disposed in inner portions thereof, and first and second conductive resin layers disposed in outer portions thereof, respectively.

Abstract: An embedded multilayer ceramic electronic component includes a ceramic body including a dielectric layer and having first and second main surfaces, first and second side surfaces, and first and second end surfaces, first and second internal electrodes, and first and second external electrodes, wherein the first external electrode includes a first base electrode electrically connected to the first internal electrode, a first intermediate layer, and a first terminal electrode, the second external electrode includes a second base electrode electrically connected to the second internal electrode, a second intermediate layer, and a second terminal electrode, the first and second base electrodes include a first conductive metal and glass, and the first and second terminal electrodes are formed of a second conductive metal.

Abstract: A multilayer ceramic capacitor may include: a ceramic body including a plurality of dielectric layers; a first capacitor part including a first internal electrode and a second internal electrode disposed in the ceramic body; second to fifth capacitor parts including a third internal electrode having a first lead, a fourth internal electrode having a second lead, a fifth internal electrode having a third lead, and a sixth internal electrode having a fourth lead, the third to sixth internal electrodes being disposed on one dielectric layer in the ceramic body, and a seventh internal electrode disposed on another dielectric layer in the ceramic body; and a first external electrode and a second external electrode. The first capacitor part and the second to fifth capacitor parts may be connected in parallel to each other.

Abstract: A multilayer ceramic capacitor may include: a ceramic body including a plurality of dielectric layers; a first capacitor part including a first internal electrode and a second internal electrode disposed in the ceramic body; second to fifth capacitor parts including a third internal electrode having first and second leads and a fourth internal electrode having third and fourth leads, the third and fourth internal electrodes being disposed on one dielectric layer in the ceramic body, and fifth and sixth internal electrodes disposed on another dielectric layer in the ceramic body; and a first external electrode and a second external electrode. The first capacitor part and the second to fifth capacitor parts may be connected in parallel to each other.

Abstract: There are provided a multilayer ceramic capacitor and a circuit board having the same. The multilayer ceramic capacitor may include: first and second internal electrodes connected to first and second external electrodes, respectively, and disposed to face each other; and third and fourth internal electrodes connected to the first and second external electrodes, respectively, and disposed to face each other, a connection area of the third and fourth internal electrodes with the first and second external electrodes being different from that of the first and second internal electrodes with the first and second external electrodes, and the first and second external electrodes including first and second conductive layers disposed in inner portions thereof and first and second conductive resin layers disposed in outer portions thereof, respectively.

Abstract: A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

Abstract: In a multilayer ceramic electronic component to be embedded in a board, a thickness of a ceramic body in an overall chip may be increased by not allowing an increase in a thickness of an external electrode to occur, while forming a band surface of the external electrode having a predetermined length or greater for connecting the external electrode to an external wiring through a via hole, thereby improving chip strength and preventing the occurrence of damage such as breakage, or the like, a manufacturing method thereof, and a printed circuit board having the multilayer ceramic electronic component.

Abstract: A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.

Abstract: A multilayer ceramic capacitor may include: a ceramic body including a plurality of dielectric layers; a first capacitor part including a first internal electrode and a second internal electrode disposed in the ceramic body; second to fifth capacitor parts including a third internal electrode having first and second leads and a fourth internal electrode having third and fourth leads, the third and fourth internal electrodes being disposed on one dielectric layer in the ceramic body, and fifth and sixth internal electrodes disposed on another dielectric layer in the ceramic body; and a first external electrode and a second external electrode. The first capacitor part and the second to fifth capacitor parts may be connected in parallel to each other.

Abstract: A multilayer ceramic capacitor may include: a ceramic body including a plurality of dielectric layers; a first capacitor part including a first internal electrode and a second internal electrode disposed in the ceramic body; second to fifth capacitor parts including a third internal electrode having a first lead, a fourth internal electrode having a second lead, a fifth internal electrode having a third lead, and a sixth internal electrode having a fourth lead, the third to sixth internal electrodes being disposed on one dielectric layer in the ceramic body, and a seventh internal electrode disposed on another dielectric layer in the ceramic body; and a first external electrode and a second external electrode. The first capacitor part and the second to fifth capacitor parts may be connected in parallel to each other.

Abstract: A sensing circuit includes a plurality of cell read current generators, a reference current generator and a plurality of sense amplifiers. Each of the cell read current generators generates a cell read current from each of a plurality of memory cells. The reference current generator sums the cell read currents to generate a sum current. Each of the sense amplifiers determines data state stored in each of the memory cells based on each of the cell read currents and an average current. The average current is obtained based on the sum current.

Abstract: A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.

Abstract: A multilayer ceramic electronic component may include a ceramic body including a dielectric layer and having first and second main surfaces, first and second side surfaces, and first and second end surfaces, a length of the ceramic body being 1300 ?m or less; a first external electrode; a second external electrode; a third external electrode; a first internal electrode connected to the first and second external electrodes; and a second internal electrode connected to the third external electrode. When a thickness of the first to third external electrodes formed on the first and second main surfaces and the first and second side surfaces is defined as to and an interval between adjacent external electrodes among the first to third external electrodes is defined as G, 5?G/te is satisfied.

Abstract: A method is for driving a nonvolatile memory device, where the nonvolatile memory device includes a memory cell array composed of resistance memory cells. The method includes electrically connecting a clamping circuit, a line resistor and a selected one of the resistance memory cells in series between a sensing node and a ground. The method further includes adjusting at least one of a clamping voltage of the clamping circuit and a resistance of the line resistor according to a relative location of the selected one of the resistance memory cells within the memory cell array, and applying a read current to the sense node and sensing a voltage of the sense node to read a data stored in the selected one of the resistance memory cells.

Abstract: There is provided an embedded multilayer ceramic electronic component including a ceramic body including a dielectric layer and having first and second main surfaces, first and second side surfaces, and first and second end surfaces, first and second internal electrodes, and first and second external electrodes, wherein the first external electrode includes a first base electrode electrically connected to the first internal electrode, a first intermediate layer, and a first terminal electrode, the second external electrode includes a second base electrode electrically connected to the second internal electrode, a second intermediate layer, and a second terminal electrode, the first and second base electrodes include a first conductive metal and glass, and the first and second terminal electrodes are formed of a second conductive metal.

Abstract: A memory device is provided, which includes a plurality of global bit lines, a discharge line, a switching circuit configured to connect the plurality of global bit lines to the discharge line in response to a discharge enable signal, a first discharge circuit configured to apply a first voltage that is higher than a ground voltage to the discharge line, a precharge circuit configured to apply a precharge voltage to a selected global bit line among the plurality of global bit lines, and a second discharge circuit configured to discharge the selected global bit line to a second voltage that is higher than the ground voltage.

Abstract: A circuit for generating a write signal includes a pre-emphasis signal generator that receives location information of a to-be-programmed memory cell and generates a pre-emphasis signal depending on the location information of the to-be-programmed memory cell, and a write driver that generates a program signal corresponding to data to be programmed in the to-be-programmed memory cell. A write signal is generated by combining the program signal with the pre-emphasis signal supplied from the pre-emphasis signal generator, and the write signal output to the to-be-programmed memory cell.

Abstract: A method is for driving a nonvolatile memory device, where the nonvolatile memory device includes a memory cell array composed of resistance memory cells. The method includes electrically connecting a clamping circuit, a line resistor and a selected one of the resistance memory cells in series between a sensing node and a ground. The method further includes adjusting at least one of a clamping voltage of the clamping circuit and a resistance of the line resistor according to a relative location of the selected one of the resistance memory cells within the memory cell array, and applying a read current to the sense node and sensing a voltage of the sense node to read a data stored in the selected one of the resistance memory cells.

Abstract: A resistive memory device includes a plurality of first switches that connect word lines to a ground line in response a first switch control signal and a plurality of second switches that connect a plurality of global bit lines to a plurality of local bit lines corresponding to the plurality of global bit lines in response to a second switch control signal.

Abstract: A semiconductor device includes; a first pad that receives an external voltage during a test, a second pad coupled to an external impedance during the test, a voltage-current converter coupled to the first pad and the second pad and generating a bias current substantially in response to only the external voltage and the external impedance, and an internal circuit responsive to a test current during the test, such that the level of the test current is defined by the level of the bias current.