Abstract: A transistor device includes a substrate, a source region provided on the substrate, a drain region in the substrate, spaced apart from the source region in a direction parallel to a top surface of the substrate, a gate electrode provided on the substrate and between the source region and the drain region, a gate insulating film interposed between the gate electrode and the substrate, and a constant current generating layer extending between the source region and the drain region, in the direction parallel to the top surface of the substrate, wherein the constant current generating layer generates a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

Abstract: A transistor device includes a substrate, a source region provided on the substrate, a drain region in the substrate, spaced apart from the source region in a direction parallel to a top surface of the substrate, a gate electrode provided on the substrate and between the source region and the drain region, a gate insulating film interposed between the gate electrode and the substrate, and a constant current generating layer extending between the source region and the drain region, in the direction parallel to the top surface of the substrate, wherein the constant current generating layer generates a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

Abstract: Disclosed herein are compounds of Formula (I): that inhibit DNA Polymerase Theta (Pol?) activity, in particular inhibit Pol? activity by inhibiting ATP dependent helicase domain activity of Pol?. Also, disclosed are pharmaceutical compositions comprising such compounds and methods of treating and/or preventing diseases treatable by inhibition of Pol? such as cancer, including homologous recombination (HR) deficient cancers.

Abstract: A polarizing plate and a display device including the same are provided. A polarizing plate includes a polarizer comprising an absorption axis and a transmission axis that intersect each other, a first retardation layer disposed on a surface of the polarizer, and a second retardation layer disposed on another surface opposite to the surface of the polarizer. An in-plane retardation value of the second retardation layer is greater than about 20 nm and less than about 100 nm. An angle between the absorption axis of the polarizer and a retardation axis of the second retardation layer is in a range of about 10° to about 45°.

Abstract: A polarizing plate and a display device including the same are provided. A polarizing plate includes a polarizer comprising an absorption axis and a transmission axis that intersect each other, a first retardation layer disposed on a surface of the polarizer, and a second retardation layer disposed on another surface opposite to the surface of the polarizer. An in-plane retardation value of the second retardation layer is greater than about 20 nm and less than about 100 nm. An angle between the absorption axis of the polarizer and a retardation axis of the second retardation layer is in a range of about 10° to about 45°.

Abstract: A transistor device includes a substrate, a source region provided on the substrate, a drain region spaced apart from the source region in a direction parallel to a top surface of the substrate, a pair of constant current generating patterns provided in the substrate to be adjacent to the source region and the drain region, respectively, a gate electrode provided on the substrate and between the source region and the drain region, and a gate insulating film interposed between the gate electrode and the substrate, wherein, the pair of constant current generating patterns generate a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

Abstract: In a memory device including a ternary memory cell, the ternary memory cell may include: a first inverter and a second inverter cross-coupled in a first node and a second node and including a pull-up device and a pull-down device configured to have a constant current pass therethrough upon turn-off; a first read transistor and a first write transistor which are connected to each other in parallel between the first node and a first bit line; and a second read transistor and a second write transistor which are connected to each other in parallel between the second node and a second bit line, wherein the first read transistor and the second read transistor may have a read access current, which is less than or equal to the constant current, pass therethrough in response to an activated read word line.

Abstract: In a memory device including a ternary memory cell, the ternary memory cell may include: a first inverter and a second inverter cross-coupled in a first node and a second node and including a pull-up device and a pull-down device configured to have a constant current pass therethrough upon turn-off; a first read transistor and a first write transistor which are connected to each other in parallel between the first node and a first bit line; and a second read transistor and a second write transistor which are connected to each other in parallel between the second node and a second bit line, wherein the first read transistor and the second read transistor may have a read access current, which is less than or equal to the constant current, pass therethrough in response to an activated read word line.

Abstract: Embodiments of a display device include a plurality of light emitting portions including a plurality of light emitting elements; and a sensing portion including a photoelectric conversion device, wherein the photoelectric conversion device includes a first electrode, common electrode facing the first electrode, and a hole injection layer, hole transport layer, resonance layer, and an active layer stacked between the first electrode and the common electrode, and wherein the light emitting elements include, a pixel electrode, the common electrode facing the pixel electrode, and the hole injection layer, hole transport layer, resonance layer, and a light emitting layer stacked between the pixel electrode and the common electrode, wherein a thickness of each of the resonance layers of light emitting elements are different from each other, and a thickness of the resonance layer of a light emitting element is the same as a thickness of the resonance layer.

Abstract: Disclosed herein are compounds of Formula (I): that inhibit DNA Polymerase Theta (Pol?) activity, in particular inhibit Pol? activity by inhibiting ATP dependent helicase domain activity of Pol?. Also, disclosed are pharmaceutical compositions comprising such compounds and methods of treating and/or preventing diseases treatable by inhibition of Pol? such as cancer, including homologous recombination (HR) deficient cancers.

Abstract: A polarizing plate and a display device including the same are provided. A polarizing plate includes a polarizer comprising an absorption axis and a transmission axis that intersect each other, a first retardation layer disposed on a surface of the polarizer, and a second retardation layer disposed on another surface opposite to the surface of the polarizer. An in-plane retardation value of the second retardation layer is greater than about 20 nm and less than about 100 nm. An angle between the absorption axis of the polarizer and a retardation axis of the second retardation layer is in a range of about 10° to about 45°.

Abstract: A transistor device includes a substrate, a fin structure extending on the substrate in a direction parallel to a top surface of the substrate, a source region and a drain region provided at an upper portion of the fin structure, a constant current generating layer provided at a lower portion of the fin structure, a gate insulating film provided on both side surfaces and a top surface of the upper portion of the fin structure, and a gate electrode provided on the gate insulating film, wherein the gate electrode is provided on the fin structure and between the source region and the drain region, the constant current generating layer generates a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

Abstract: A transistor device includes a substrate, a fin structure extending on the substrate in a direction parallel to a top surface of the substrate, a source region and a drain region provided at an upper portion of the fin structure, a constant current generating layer provided at a lower portion of the fin structure, a gate insulating film provided on both side surfaces and a top surface of the upper portion of the fin structure, and a gate electrode provided on the gate insulating film, wherein the gate electrode is provided on the fin structure and between the source region and the drain region, the constant current generating layer generates a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

Abstract: According to an embodiment of the present disclosure, a memory device for a logic-in-memory may include a cell array including a plurality of ternary memory cells, a row decoder configured to select at least one ternary memory cell from among the plurality of ternary memory cells, and a page buffer configured to provide a first value to the at least one ternary memory cell and latch a third value obtained by performing a logic operation on the first value and a second value stored in the at least one ternary memory cell and/or the second value.

Abstract: A transistor device includes a substrate, a source region provided on the substrate, a drain region in the substrate, spaced apart from the source region in a direction parallel to a top surface of the substrate, a gate electrode provided on the substrate and between the source region and the drain region, a gate insulating film interposed between the gate electrode and the substrate, and a constant current generating layer extending between the source region and the drain region, in the direction parallel to the top surface of the substrate, wherein the constant current generating layer generates a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

Abstract: A transistor device includes a substrate, a fin structure extending on the substrate in a direction parallel to a top surface of the substrate, a source region and a drain region provided at an upper portion of the fin structure, a constant current generating layer provided at a lower portion of the fin structure, a gate insulating film provided on both side surfaces and a top surface of the upper portion of the fin structure, and a gate electrode provided on the gate insulating film, wherein the gate electrode is provided on the fin structure and between the source region and the drain region, the constant current generating layer generates a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

Abstract: A transistor device includes a substrate, a source region provided on the substrate, a drain region spaced apart from the source region in a direction parallel to a top surface of the substrate, a pair of constant current generating patterns provided in the substrate to be adjacent to the source region and the drain region, respectively, a gate electrode provided on the substrate and between the source region and the drain region, and a gate insulating film interposed between the gate electrode and the substrate, wherein, the pair of constant current generating patterns generate a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

Abstract: According to an embodiment of the present disclosure, a memory device for a logic-in-memory may include a cell array including a plurality of ternary memory cells, a row decoder configured to select at least one ternary memory cell from among the plurality of ternary memory cells, and a page buffer configured to provide a first value to the at least one ternary memory cell and latch a third value obtained by performing a logic operation on the first value and a second value stored in the at least one ternary memory cell and/or the second value.

Abstract: In a memory device including a ternary memory cell, the ternary memory cell may include: a first inverter and a second inverter cross-coupled in a first node and a second node and including a pull-up device and a pull-down device configured to have a constant current pass therethrough upon turn-off; a first read transistor and a first write transistor which are connected to each other in parallel between the first node and a first bit line; and a second read transistor and a second write transistor which are connected to each other in parallel between the second node and a second bit line, wherein the first read transistor and the second read transistor may have a read access current, which is less than or equal to the constant current, pass therethrough in response to an activated read word line.

Abstract: An inspection apparatus for detecting a defect of a substrate is provided. The inspection apparatus includes a liquid crystal modulator, a light emitting unit, a beam splitter, and a measurement unit. The liquid crystal modulator includes a reflection layer, a liquid crystal layer, an electrode, and a polarizer. The reflection layer reflects a light. The sensor layer includes a hybrid aligned nematic liquid crystal. The electrode is provided on the liquid crystal layer. The polarizer is provided on the electrode.