Abstract: A rotary device having mounted therein a drill for soil earthwork. The drill includes a shaft and a screw, formed along the outer circumferential surface of the shaft, for earthwork and the transportation of displaced soil. A rotary shaft is formed on the upper part of the shaft. A fixed shaft part is formed on the lower part of the shaft, for being inserted and rotated into the soil. A pair of horizontal blades face each other on the connection part between the shaft and the fixed shaft part. Cutting blades, which are symmetrical with each other, incline downwardly on the pair of horizontal blades. Vertical blades protrude vertically on the upper portion of the lower wing of the screw and, when performing earthwork, soil and tree roots are cut by the cutting blades, and soil lumps, transferred along the screw, are cut again by the vertical blades.

Abstract: An apparatus comprising a plurality of devices connected in series with one another, each of the devices comprising a test enable pin for receiving a test enable signal that indicates enablement of a test mode, and a test output pin for outputting a test output signal in the test mode, and a controller coupled to the devices and comprising an additional test output pin for outputting a test channel output signal, wherein a failure of at least one of the test output signals and the test channel output signal indicates the existence of one or more potential defects associated with the plurality of devices and the controller.

Abstract: A memory controller of a data storage device, which communicates with a host, is configurable to have at least two different pinout assignments for interfacing with respective different types of memory devices. Each pinout assignment corresponds to a specific memory interface protocol. Each memory interface port of the memory controller includes port buffer circuitry configurable for different functional signal assignments, based on the selected memory interface protocol to be used. The interface circuitry configuration for each memory interface port is selectable by setting a predetermined port or registers of the memory controller.

Abstract: Provided is a controller for a solid state disk, to control simultaneous switching of pads. The controller for the solid state disk may control simultaneous switching of a plurality of output pads or a plurality of input pads that correspond to a plurality of channels. In particular, the controller may properly delay signals driven to the output pads or input pads, to reduce power supplied to the pads, and to prevent ground bouncing, as well as, maintain a quality of signals.

Abstract: An apparatus comprising a plurality of devices connected in series with one another, each of the devices comprising a test enable pin for receiving a test enable signal that indicates enablement of a test mode, and a test output pin for outputting a test output signal in the test mode, and a controller coupled to the devices and comprising an additional test output pin for outputting a test channel output signal, wherein a failure of at least one of the test output signals and the test channel output signal indicates the existence of one or more potential defects associated with the plurality of devices and the controller.

Abstract: A Solid State Drive (SSD) controller is disclosed. When a data read command is transmitted by a host, the SSD controller may select a representative pointer from at least one first pointer by checking a point in time when data writing is completed in a buffer by at least one memory, read the data from the buffer by referring to a second pointer, and transmit the read data to the host, based on the representative pointer.

Abstract: A memory controller of a data storage device which communicates with a host, has channel control modules each being configurable to have at three different pinout assignments for interfacing with two different types of memory devices operating with different memory interface protocols. One pinout assignment corresponds to a memory interface protocol where memory devices can be connected in parallel with each other. Two other pinout assignments correspond respectively to inbound and outbound signals of another memory interface protocol where memory devices are serially connected with each other. In this mode of operation, one channel control module is configured to provide the outbound signals while another channel control module is configured to receive the inbound signals. Each memory port of the channel control modules includes port buffer circuitry configurable for different functional signal assignments.

Abstract: A memory controller of a data storage device, which communicates with a host, is configurable to have at least two different pinout assignments for interfacing with respective different types of memory devices. Each pinout assignment corresponds to a specific memory interface protocol. Each memory interface port of the memory controller includes port buffer circuitry configurable for different functional signal assignments, based on the selected memory interface protocol to be used. The interface circuitry configuration for each memory interface port is selectable by setting a predetermined port or registers of the memory controller.

Abstract: Disclosed are a semiconductor memory system and a method for controlling same. The semiconductor memory system according to one embodiment of the present invention includes: a first memory for storing normal data and master metadata, the master metadata representing a relationship between a local address and a physical address for accessing the normal data; and a control logic generating compression metadata compressed in accordance with update metadata and storing the generated metadata in the first memory in response to a first control signal.

Abstract: A semiconductor chip and a semiconductor system comprising the chip. The semiconductor system comprises: a serial advanced technology attachment (SATA) host; a plurality of SATA devices which receive data from the SATA host and stores the received data, or transmit the stored data to the SATA host; and a semiconductor chip which controls a data-transceiving operation between the SATA host and the SATA devices. The semiconductor chip and the semiconductor system have merits in that the semiconductor chip may be connected to a plurality of devices without being limited by the number of host channels of the semiconductor chip, while preventing an increase in the size of a host.

Abstract: The present invention relates to a portable storage device communicating via a USB 3.0 protocol and a computer system having the same. The computer system according to one embodiment of the present invention comprises a portable storage device and a computer. The portable storage device includes an operating system (OS) storage region for storing OS data and boot data which are not sent to the computer through a transmission channel used for data transmission via the USB 3.0 protocol, requested by a receiving channel used for receiving data via the USB 3.0 protocol, and loaded on the computer to drive the computer.

Abstract: Disclosed are a semiconductor memory system having semiconductor memory devices of various types and a control method for the same. A semiconductor memory system according to an embodiment of the present invention comprises a plurality of semiconductor memory devices; and a memory controller for controlling the read-out of data programs for the plurality of semiconductor memory devices and data from the plurality of semiconductor memory devices, wherein at least two of the plurality of semiconductor memory devices differ from each other in terms of one or more of the following: the number of bits of data programmed in memory cells, the degree of integration, the manufacturer, whether they are synchronized, and whether or not encoded data is stored.

Abstract: A Solid State Drive (SSD) controller is disclosed. When a data read command is transmitted by a host, the SSD controller may select a representative pointer from at least one first pointer by checking a point in time when data writing is completed in a buffer by at least one memory, read the data from the buffer by referring to a second pointer, and transmit the read data to the host, based on the representative pointer.

Abstract: An apparatus and method for managing a dynamic random access memory (DRAM) buffer are disclosed. The DRAM buffer managing apparatus and method may generate an error correction code (ECC) for data to be written in a DRAM buffer, and may write the data and the ECC in the DRAM buffer.

Abstract: Provided is a controller for a solid state disk, to control simultaneous switching of pads. The controller for the solid state disk may control simultaneous switching of a plurality of output pads or a plurality of input pads that correspond to a plurality of channels. In particular, the controller may properly delay signals driven to the output pads or input pads, to reduce power supplied to the pads, and to prevent ground bouncing, as well as, maintain a quality of signals.

Abstract: A method for decoding data stored in a disk is achieved by demodulating a physical cluster read out from the disk and outputting LDC (long distance code) data and BIS (burst indicator subcode) data included in the physical cluster, temporarily storing part of the LDC data and BIS data of the data included in the physical cluster in a first memory portion, reading out the LDC data and BIS data stored in the first memory portion and storing the read out data in a second memory portion, reading out LDC data and BIS data requiring error correction from the second memory portion and temporarily storing the read out data in the first memory portion, and storing LDC data and BIS data for which data processing operation including the error correction operation is completed in the second memory portion.

Abstract: Disk players for allocating pointers to the respective frames of CD data and storing the pointers in a memory, and methods of processing reproduced data of the disk player are provided. According to one aspect, a disk player includes a pointer controller, which allocates pointers to frames of recorded data read from a disk, wherein the allocation of the pointers starts from a first frame following frames having special sub-code synchronization signals and is performed in a predetermined order; a memory, which stores the frames and the allocated pointers; and a memory controller, which controls an operation of writing the data to memory. A pointer is allocated to every frame of the recorded data reproduced from the disk player, and the allocated pointers and the frame data are stored in the memory. The pointers are retrieved and the respective frame data stored in the memory are output. Therefore, the sound continuity can be maintained even in a vibration environment causing jitter.

Abstract: A method for decoding data stored in a disk is achieved by demodulating a physical cluster read out from the disk and outputting LDC (long distance code) data and BIS (burst indicator subcode) data included in the physical cluster, temporarily storing part of the LDC data and BIS data of the data included in the physical cluster in a first memory portion, reading out the LDC data and BIS data stored in the first memory portion and storing the read out data in a second memory portion, reading out LDC data and BIS data requiring error correction from the second memory portion and temporarily storing the read out data in the first memory portion, and storing LDC data and BIS data for which data processing operation including the error correction operation is completed in the second memory portion.

Abstract: Disk players for allocating pointers to the respective frames of CD data and storing the pointers in a memory, and methods of processing reproduced data of the disk player are provided. According to one aspect, a disk player includes a pointer controller, which allocates pointers to frames of recorded data read from a disk, wherein the allocation of the pointers starts from a next frame after frames having sub-code synchronization signals and is performed in a predetermined order; a memory, which stores the frames and the allocated pointers; and a memory controller, which controls an operation of writing the data to memory. A pointer is allocated to every frame of the recorded data reproduced from the disk player, and the allocated pointers and the frame data are stored in the memory. The pointers are retrieved and the respective frame data stored in the memory are output. Therefore, the sound continuity can be maintained even in a jitter environment causing vibration.

Abstract: A variable length code decoder for MPEG (Motion Picture Expert Group) includes a barrel shifter for outputting the bit stream being decoded, a register for storing the output data of the barrel shifter, a finite state machine for parsing the output data of the barrel shifter and determining whether the data is an ordinary data or a more than 16-bit data, and outputs resultant control signals, a multiplexer for selectively outputting the output data of the barrel shifter or the register based on the control signal, and a decoding units for decoding a variable length code, a header code of a MPEG2 syntax from the output of the multiplexer in accordance with the control signal of the finite state machine. The variable length code decoder obtains a data throughput rate equivalent to the using of 32-bit data path.