Patents by Inventor Young Gue Lee
Young Gue Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240067208Abstract: There is provided a VIL system-based autonomous driving function verification method. According to embodiments of the disclosure, a VIL system enables an autonomous vehicle to verify an autonomous driving function by interlocking with a virtual road environment in any other place, without having to go to a real test road corresponding to a simulated virtual road environment. Accordingly, an autonomous driving function can be rapidly verified based on a VIL system with respect to various virtual road environments without changing a driving place, so that speed and convenience in development of autonomous driving technology can be enhanced.Type: ApplicationFiled: April 21, 2023Publication date: February 29, 2024Inventors: Young Bo SHIM, Kyoung Won MIN, Haeng Seon SON, Seon Young LEE, Chang Gue PARK
-
Publication number: 20140346654Abstract: A chip package comprising a carrier, a chip, a plurality of first conductive elements, an encapsulation, and a conductive film is provided. The carrier has a carrying surface and a back surface opposite to the carrying surface. Furthermore, the carrier has a plurality of common contacts in the periphery of the carrying surface. The chip is disposed on the carrying surface and electrically connected to the carrier. In addition, the first conductive elements are disposed on the common contacts respectively. The encapsulation is disposed on the carrying surface and encapsulating the chip. Moreover, the conductive film is disposed over the encapsulation and the first conductive elements, so as to electrically connect with the common contacts via the first conductive elements. A process for fabricating the chip package is further provided. The chip package is capable of preventing the EMI problem and thus provides superior electrical performance.Type: ApplicationFiled: June 2, 2014Publication date: November 27, 2014Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Soo-Min CHOI, Hyeong-No KIM, Jae-Sun AN, Young-Gue LEE, Sang-Jin CHA
-
Patent number: 8866280Abstract: A chip package comprising a carrier, a chip, a plurality of first conductive elements, an encapsulation, and a conductive film is provided. The carrier has a carrying surface and a back surface opposite to the carrying surface. Furthermore, the carrier has a plurality of common contacts in the periphery of the carrying surface. The chip is disposed on the carrying surface and electrically connected to the carrier. In addition, the first conductive elements are disposed on the common contacts respectively. The encapsulation is disposed on the carrying surface and encapsulating the chip. Moreover, the conductive film is disposed over the encapsulation and the first conductive elements, so as to electrically connect with the common contacts via the first conductive elements. A process for fabricating the chip package is further provided. The chip package is capable of preventing the EMI problem and thus provides superior electrical performance.Type: GrantFiled: June 25, 2009Date of Patent: October 21, 2014Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Soo-Min Choi, Hyeong-No Kim, Jae-Sun An, Young-Gue Lee, Sang-Jin Cha
-
Patent number: 7964952Abstract: A stackable package substrate has an opening shaped and dimensioned to accommodate but not contact a mold cap of a package upon which the stackable package is to be mounted. On the die attach surface, the frame substrate accommodates a die attach margin adjacent at the edge of the opening; and a row of wire bond sites arranged along at an outer frame edge, for electrical interconnection. The frame substrate accommodates z-interconnect ball pads arranged to align with corresponding z-interconnect pads on the substrate of a package. A stackable package has a frame substrate. A stacked package assembly includes a second package mounted on a first package using peripheral solder ball z-interconnect, in which the first package includes a die enclosed by a mold cap and in which the second package includes one die mounted on the frame substrate.Type: GrantFiled: March 24, 2009Date of Patent: June 21, 2011Assignee: Stats Chippac Ltd.Inventor: Young Gue Lee
-
Publication number: 20090261470Abstract: A chip package comprising a carrier, a chip, a plurality of first conductive elements, an encapsulation, and a conductive film is provided. The carrier has a carrying surface and a back surface opposite to the carrying surface. Furthermore, the carrier has a plurality of common contacts in the periphery of the carrying surface. The chip is disposed on the carrying surface and electrically connected to the carrier. In addition, the first conductive elements are disposed on the common contacts respectively. The encapsulation is disposed on the carrying surface and encapsulating the chip. Moreover, the conductive film is disposed over the encapsulation and the first conductive elements, so as to electrically connect with the common contacts via the first conductive elements. A process for fabricating the chip package is further provided. The chip package is capable of preventing the EMI problem and thus provides superior electrical performance.Type: ApplicationFiled: June 25, 2009Publication date: October 22, 2009Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Soo-Min Choi, Hyeong-No Kim, Jae-Sun An, Young-Gue Lee, Sang-Jin Cha
-
Publication number: 20090179319Abstract: A stackable package substrate has an opening shaped and dimensioned to accommodate but not contact a mold cap of a package upon which the stackable package is to be mounted. On the die attach surface, the frame substrate accommodates a die attach margin adjacent at the edge of the opening; and a row of wire bond sites arranged along at an outer frame edge, for electrical interconnection. The frame substrate accommodates z-interconnect ball pads arranged to align with corresponding z-interconnect pads on the substrate of a package. A stackable package has a frame substrate. A stacked package assembly includes a second package mounted on a first package using peripheral solder ball z-interconnect, in which the first package includes a die enclosed by a mold cap and in which the second package includes one die mounted on the frame substrate.Type: ApplicationFiled: March 24, 2009Publication date: July 16, 2009Inventor: Young Gue Lee
-
Patent number: 7528474Abstract: A stackable package substrate has an opening shaped and dimensioned to accommodate a mold cap of a package upon which the stackable package is to be mounted. On the die attach surface, the frame substrate accommodates a die attach margin adjacent at the edge of the opening; and a row of wire bond sites arranged along at an outer frame edge, for electrical interconnection. The frame substrate accommodates z-interconnect ball pads arranged to align with corresponding z-interconnect pads on the substrate of a package. A stackable package has a frame substrate. A stacked package assembly includes a second package mounted on a first package using peripheral solder ball z-interconnect, in which the first package includes a die enclosed by a mold cap and in which the second package includes one die mounted on the frame substrate.Type: GrantFiled: May 30, 2006Date of Patent: May 5, 2009Assignee: Stats Chippac Ltd.Inventor: Young Gue Lee
-
Publication number: 20080237820Abstract: A package structure including a substrate, a shielding element, a chip, a sealant layer and a semiconductor device is provided. The substrate has a first surface and a second surface opposite to the first surface. The shielding element is disposed on the first surface. The chip is disposed on the shielding element and is electrically connected to the substrate. The sealant layer is disposed on the first surface, and encapsulates the chip and the shielding element. The semiconductor device is disposed on the second surface.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Inventors: Hyeongno Kim, Soo-Min Choi, Jae-Sun An, Young-Gue Lee, Sang-Jin Cha
-
Publication number: 20080237821Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a substrate, a shielding plate, a first chip, a first sealant, a second chip and a second sealant. The substrate has a lower surface and an upper surface on which the shielding plate is disposed. The first chip disposed on the shielding plate is electrically connected to the substrate. The first sealant disposed on the upper surface encapsulates the shielding plate and the first chip. The second chip disposed on the lower surface is electrically connected to the substrate. The second sealant disposed on the lower surface encapsulates the second chip.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Inventors: Hyeongno Kim, Soo-Min Choi, Jae-Sun An, Young-Gue Lee, Sang-Jin Cha
-
Publication number: 20080197468Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a substrate, a first chip, a cap structure, a second chip and a sealant. The first chip is disposed in an opening of the substrate and is electrically connected to the substrate. The cap structure is disposed on the substrate corresponding to the first chip. The second chip is disposed on the cap structure and is electrically connected to the substrate. The sealant encapsulates the first chip, the cap structure and the second chip.Type: ApplicationFiled: February 15, 2007Publication date: August 21, 2008Inventors: Hyeongno Kim, Soo-Min Choi, Jae-Sun An, Young-Gue Lee, Sang-Jin Cha
-
Publication number: 20080128890Abstract: A chip package comprising a carrier, a chip, a plurality of first conductive elements, an encapsulation, and a conductive film is provided. The carrier has a carrying surface and a back surface opposite to the carrying surface. Furthermore, the carrier has a plurality of common contacts in the periphery of the carrying surface. The chip is disposed on the carrying surface and electrically connected to the carrier. In addition, the first conductive elements are disposed on the common contacts respectively. The encapsulation is disposed on the carrying surface and encapsulating the chip. Moreover, the conductive film is disposed over the encapsulation and the first conductive elements, so as to electrically connect with the common contacts via the first conductive elements. A process for fabricating the chip package is further provided. The chip package is capable of preventing the EMI problem and thus provides superior electrical performance.Type: ApplicationFiled: November 30, 2006Publication date: June 5, 2008Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: SOO-MIN CHOI, HYEONG-NO KIM, JAE-SUN AN, YOUNG-GUE LEE, SANG-JIN CHA