Abstract: A semiconductor device includes source/drain regions formed over a substrate, and channel patterns and gate structures formed between the source/drain regions in a horizontal direction. The channel patterns are arranged to be spaced apart from each other over a surface of the substrate in a vertical direction. The gate structures are disposed between the channel patterns in the vertical direction. The gate structures include the following: side spacer patterns formed adjacent to the source/drain regions in the first horizontal direction, interfacial insulating layers formed over upper and lower surfaces of the channel patterns, gate insulating layers over surfaces of the side spacer patterns and surfaces of the interfacial insulating layers, and gate electrodes over the gate insulating layers. The side spacer patterns include germanium (Ge).

Abstract: A semiconductor device includes a buried gate structure including: a gate trench formed in a substrate; a gate insulating layer conformally formed over a bottom surface and an inner wall of the gate trench; a dipole inducing layer conformally formed over a bottom surface and an inner wall of the gate insulating layer; a dipole diffusion barrier layer conformally formed over a bottom surface and an inner wall of the dipole inducing layer; and a gate electrode formed over the dipole diffusion barrier layer to fill a lower region of the gate trench.

Abstract: A semiconductor device includes an inter-layer dielectric layer over a substrate; a first contact plug structure coupled to a first active region of the substrate by vertically penetrating the inter-layer dielectric layer, and a second contact plug structure coupled to a second active region of the substrate. The first contact plug structure includes a first metal silicide layer; a first contact barrier layer over the first metal silicide layer; and a first contact plug over the first contact barrier layer. The second metal plug structure includes a second metal silicide layer; a second contact barrier layer over the second contact silicide layer; and a second contact plug over the second contact barrier layer. The first and second metal silicide layers include different metal silicides. The first metal silicide layer has a wider horizontal width and a greater vertical height than the second metal silicide layer.

Abstract: Various embodiments of the present invention disclosure are directed to a vertical transistor having different doping profiles in its upper channel layer and lower channel layer for reducing leakage current while enhancing contact resistance and a method for manufacturing the vertical transistor. According to an embodiment of the present invention disclosure, a semiconductor device comprises a lower contact, a vertical channel layer on the lower contact, the vertical channel layer including a metal component and an oxygen component, and an upper contact on the vertical channel layer. The vertical channel layer has a gradual doping profile in which a doping concentration of the metal component is lowest in an intermediate region and gradually increases from the intermediate region to the upper contact.

Abstract: A semiconductor device includes: a first stacked structure including a first lower dielectric layer, a first horizontal gate structure, and a first upper dielectric layer stacked vertically; a second stacked structure including a second lower dielectric layer, a second horizontal gate structure, and a second upper dielectric layer stacked vertically, and having a first side facing a first side of the first stacked structure; a first channel layer formed on the first side of the first stacked structure; a second channel layer formed on the first side of the second stacked structure; a lower electrode layer commonly coupled to lower ends of the first and second channel layers between the first and second stacked structures; a first upper electrode layer coupled to an upper end of the first channel layer; and a second upper electrode layer coupled to an upper end of the second channel layer.

Abstract: The present invention provides a semiconductor device including a capping layer of a reduced thickness and capable of preventing regrowth of an interface layer caused by oxygen injection, and a method for fabricating the same. According to an embodiment of the present invention, the semiconductor device comprises: an interface layer on a substrate; a high-k layer on the interface layer; a gate electrode on the high-k layer; and a capping layer including a first oxygen barrier layer and a second oxygen barrier layer on the gate electrode.

Abstract: A 3D semiconductor device includes: a word line stack over a substrate; and a channel pillar vertically penetrating the word line stack. The word line stack includes a word line and an interlayer dielectric layer. The channel pillar includes: a central dielectric layer; a channel layer surrounding a side of the central dielectric layer; a tunneling dielectric layer having a cylinder shape surrounding a side of the channel layer; an inner charge trap layer surrounding a side of the tunneling dielectric layer; a ring-shaped outer charge trap layer surrounding a side of the inner charge trap layer; and a ring-shaped blocking dielectric layer surrounding a side of the outer charge trap layer. The word line and the blocking dielectric layer have substantially the same vertical thickness. The interlayer dielectric layer is in contact with upper and lower surfaces of the outer charge trap layer and the blocking dielectric layer.

Abstract: Various embodiments of the present invention are to provide a semiconductor device and a method for fabricating the same and, more particularly, to a semiconductor device including isolation layers including an air gap, thereby minimizing stress to a substrate caused by oxide and improving performance of a device, and a method for fabricating the same. The semiconductor device according to the embodiment of the present invention comprises: a plurality of isolation layers each including a trench formed in a substrate and an air gap in a lower portion of the trench; an active region including a fin body disposed between the isolation layers, which are consecutively disposed, and a fin formed on the fin body, the fin having a narrower width than the fin body and extending in a first direction; a gate structure partially covering the active region and the isolation layers, and extending in a second direction; and a source/drain region covering the fin on both sides of the gate structure.

Abstract: A semiconductor device includes a first gate stack and a second gate stack disposed on a substrate. The first gate stack includes a first lower gate insulating layer. The second gate stack includes a second lower gate insulating layer. The first lower gate insulating layer includes silicon oxide with a first dipole material. The second lower gate insulating layer includes silicon oxide with a second dipole material. The first dipole material and the second dipole material are different from each other.

Abstract: A semiconductor device includes a gate dielectric layer over a substrate; a lower gate barrier layer over the gate dielectric layer; and a lower gate electrode over the lower gate barrier layer. The lower gate electrode includes at least one metal-rich metal oxide layer.

Abstract: Various embodiments of the present invention are to provide a semiconductor device and a method for fabricating the same and, more particularly, to a semiconductor device including isolation layers including an air gap, thereby minimizing stress to a substrate caused by oxide and improving performance of a device, and a method for fabricating the same. The semiconductor device according to the embodiment of the present invention comprises: a plurality of isolation layers each including a trench formed in a substrate and an air gap in a lower portion of the trench; an active region including a fin body disposed between the isolation layers, which are consecutively disposed, and a fin formed on the fin body, the fin having a narrower width than the fin body and extending in a first direction; a gate structure partially covering the active region and the isolation layers, and extending in a second direction; and a source/drain region covering the fin on both sides of the gate structure.

Abstract: A method for fabricating a semiconductor device may include: forming a gate dielectric material over a substrate; sequentially forming a carbon-undoped polysilicon layer and a carbon-doped polysilicon layer over the gate dielectric material; doping the carbon-doped polysilicon layer with a dopant; forming a columnar crystalline polysilicon layer over the carbon-doped polysilicon layer doped with the dopant; and performing annealing to activate the dopant.

Abstract: A semiconductor device includes a word line stack over a substrate, the word line stack including a plurality of interlayer insulating layers and a plurality of word lines alternatively stacked, and a vertical channel pillar vertically passing through the word line stack. The vertical channel pillar includes a core insulating layer, a channel layer surrounding a side surface of the core insulating layer, and a memory layer surrounding a side surface of the channel layer. The channel layer includes a silicide channel layer and a silicon channel layer surrounding a side surface of the silicide channel layer.

Abstract: A semiconductor device include a substrate having a gate area and a contact area, a buried insulating layer formed over the substrate, a fin-type insulating pattern formed over the buried insulating layer and extending in a first horizontal direction, a lower metal layer covering an upper surface and side surfaces of the fin-type insulating pattern in the contact pattern, a channel layer covering an upper surface and side surfaces of the lower metal layer in the contact area and covering the upper surface and the side surfaces of the fin-type insulating pattern in the gate area, a gate pattern disposed over the channel layer in the gate area and extending in a second direction, and a source/drain contact pattern disposed over the channel layer in the contact area. The lower metal layer includes a Ti-based metal. The channel layer includes an oxide semiconductor material.

Abstract: A semiconductor device includes a substrate, a buried insulating layer on the substrate, a channel layer and a source/drain layer on the buried insulating layer, and a gate electrode pattern on the channel layer. The channel layer and the source/drain layer include an oxide semiconducting material. An oxygen vacancy concentration in the source/drain layer is higher than an oxygen vacancy concentration in the channel layer.

Abstract: Embodiments of the present disclosure provide a FinFET. The FinFET may include fin-type active regions protruding from a substrate, the fin-type active regions extending in a first direction, a field insulating layer on a surface of the substrate between the fin-type active regions, and gate structures disposed on surfaces of the fin-type active regions and a surface of the field insulating layer, the gate structures extending in a second direction perpendicular to the first direction. Each of the gate structures may include a gate dielectric layer conformally disposed on the surfaces of the fin-type regions and a gate electrode on the gate dielectric layer. The gate electrode may include low concentration impurity regions close to the field insulating layer, and high concentration impurity regions close to an upper portion of the fin-type active regions.

Abstract: A method for fabricating a MOS transistor includes: forming a gate dielectric material layer over a substrate; forming a lower gate electrode material layer over the gate dielectric material layer; performing a first ion bombardment process of bombarding the lower gate electrode material layer with first ions; forming an intermediate gate electrode material layer including an amorphous silicon layer over the lower gate electrode material layer; forming an upper gate electrode material layer over the intermediate gate electrode material layer; performing a second ion bombardment process for bombarding the upper gate electrode material layer with second ions; and forming silicide layers in the lower gate electrode material layer and the upper gate electrode material layer to form a lower gate electrode layer and an upper gate electrode layer.

Abstract: Embodiments of the present invention provide a semiconductor device capable of improving both the thermal stability and contact resistance and a method for fabricating the same. According to an embodiment of the present invention, a semiconductor device may comprise: a contact plug over a substrate, wherein the contact plug includes: a silicide layer having a varying carbon content in a film, and a metal material layer over the silicide layer.

Abstract: The present invention provides a semiconductor device including a capping layer of a reduced thickness and capable of preventing regrowth of an interface layer caused by oxygen injection, and a method for fabricating the same. According to an embodiment of the present invention, the semiconductor device comprises: an interface layer on a substrate; a high-k layer on the interface layer; a gate electrode on the high-k layer; and a capping layer including a first oxygen barrier layer and a second oxygen barrier layer on the gate electrode.

Abstract: A semiconductor device includes: a first stacked structure including a first lower dielectric layer, a first horizontal gate structure, and a first upper dielectric layer stacked vertically; a second stacked structure including a second lower dielectric layer, a second horizontal gate structure, and a second upper dielectric layer stacked vertically, and having a first side facing a first side of the first stacked structure; a first channel layer formed on the first side of the first stacked structure; a second channel layer formed on the first side of the second stacked structure; a lower electrode layer commonly coupled to lower ends of the first and second channel layers between the first and second stacked structures; a first upper electrode layer coupled to an upper end of the first channel layer; and a second upper electrode layer coupled to an upper end of the second channel layer.