Abstract: An integrated circuit includes a first driving unit configured to drive an output terminal to a first power supply voltage in response to an active mode signal, a second driving unit configured to drive the output terminal to a second power supply voltage in response to a standby mode signal, and a current control unit configured to control the current path between the first driving unit and the first power supply voltage terminal in response to a mode control signal denoting the active mode signal and the standby mode signal.

Abstract: The present invention provides a polyimide film which is both outstandingly transparent and highly heat resistance, and which can be usefully employed as a transparent electrically conductive film, a TFT substrate, a flexible printed circuit substrate, and the like.

Abstract: The present invention provides a polyimide film having a good transparency and also an excellent thermal resistance so that it is useful in a transparent conductive film, TFT substrate, a flexible printing circuit substrate, and the like.

Abstract: A semiconductor memory device includes a fuse set configured to form a current path including at least one of a plurality of fuses in response to address information corresponding to a plurality of memory cells and to output a redundancy address corresponding to a programming state of the plurality of fuses where the plurality of fuses are programmed with address information corresponding to a target memory cell to be repaired among the plurality of memory cells, and at least one current controlling unit configured to control a driving current flowing through the current path according to at least one detection signal.

Abstract: Disclosed is a polyimide film, which is very transparent and very resistant to heat and thus undergoes little dimensional change under thermal stress, and is suitable for use in transparent conductive films, TFT substrates, flexible printed circuit boards and so on.

Abstract: A semiconductor memory apparatus according to an embodiment of the invention includes a delay enable unit that generates a delay enable signal in response to an external ODT signal and an idle signal, a delay selecting unit that outputs the idle signal or a delay idle signal, which is obtained by delaying the idle signal by a first delay time, in response to the delay enable signal, and a DLL clock control unit that generates a control signal in response to the idle signal or the delay idle signal during a slow power down exit mode.

Abstract: A semiconductor memory device includes a fuse set configured to form a current path including at least one of a plurality of fuses in response to address information corresponding to a plurality of memory cells and to output a redundancy address corresponding to a programming state of the plurality of fuses where the plurality of fuses are programmed with address information corresponding to a target memory cell to be repaired among the plurality of memory cells, and at least one current controlling unit configured to control a driving current flowing through the current path according to at least one detection signal.

Abstract: The semiconductor memory device includes a plurality of bank groups each including a plurality of banks sharing one of a plurality of global input/output line groups, a data input unit configured to transfer external data to data input global lines in response to write commands corresponding to the respective bank groups, a data output unit configured to output data applied on data output global lines to an external circuit in response to read commands corresponding to the respective bank groups, and a data transfer unit configured to transfer data applied on the data input global lines to one of the plurality of global input/output line groups in response to the write commands, and to transfer data applied on one of the plurality of global input/output line groups to the data output global lines in response to the read commands.

Abstract: A semiconductor memory apparatus according to an embodiment of the invention includes a delay enable unit that generates a delay enable signal in response to an external ODT signal and an idle signal, a delay selecting unit that outputs the idle signal or a delay idle signal, which is obtained by delaying the idle signal by a first delay time, in response to the delay enable signal, and a DLL clock control unit that generates a control signal in response to the idle signal or the delay idle signal during a slow power down exit mode.

Abstract: The semiconductor memory device includes a plurality of band groups each including a plurality of banks sharing one of a plurality of global input/output line groups, a data input unit configured to transfer external data to data input global lines in response to write commands corresponding to the respective bank groups, a data output unit configured to output data applied on data output global lines to an external circuit in response to read commands corresponding to the respective bank groups, and a data transfer unit configured to transfer data applied on the data input global lines to one of the plurality of global input/output line groups in response to the write commands, and to transfer data applied on one of the plurality of global input/output line groups to the data output global lines in response to the read commands.

Abstract: A circuit is provided that generates a sense amplifier control signal for a semiconductor memory in which signal paths for a normal operation and a refresh operation are separately formed so that a pulse width of an overdriving interval in the refresh operation is reduced. The reduced overdriving interval in the refresh operation reduces a refresh current. The circuit for generating the sense amplifier control signal for a semiconductor memory circuit can include a first delay that delays a sense amplifier enable signal for a first delay time, a second delay that delays an output signal from the first delay for a second delay time and a logic unit that receives output signals from the first delay and from the second delay and operates in normal operations and refresh operations in accordance with a refresh control signal to perform a logic operation on the output signals of the first and second delays, so that the overdriving interval is set shorter for the refresh operation relative to the normal operation.

Abstract: A RC delay time stabilizing circuit of the present invention includes an inverter which inverts a periodic input signal, a RC delay unit which is charged/discharged in accordance with an output from the inverter, a pull-up MOS transistor connected between a source voltage terminal and an output terminal of the RC delay unit and having a gate for receiving the input signal, and an output unit which generates an output signal having an identical delay time in accordance with output levels of the inverter and the RC delay unit. Such RC delay time stabilizing circuit of the present invention decreases the charging time of the RC delay unit when a periodic signal is inputted, thus being able to maintain the same delay time in each cycle of the input signal.