Patents by Inventor Young Hee Mun

Young Hee Mun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8597756
    Abstract: Provided are a resistance heated sapphire single crystal ingot grower, a method of manufacturing a resistance heated sapphire single crystal ingot, a sapphire single crystal ingot, and a sapphire wafer. The resistance heated sapphire single crystal ingot grower comprises according to an embodiment includes a chamber, a crucible included in the chamber and containing an alumina melt, and a resistance heating heater included inside the chamber and heating the crucible.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: December 3, 2013
    Assignee: LG Siltron Inc.
    Inventors: Do Won Song, Young Hee Mun, Sang Hoon Lee, Seong Oh Jeong, Chang Youn Lee
  • Publication number: 20130115859
    Abstract: Provided is a surface treatment method of a polishing pad. The surface treatment method of the polishing pad includes locating a wafer on the polishing pad including a polishing material, supplying a polishing pad polishing material between the polishing pad and the wafer to expose the polishing material included in the polishing pad, and polishing the wafer using the exposed polishing material.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 9, 2013
    Inventors: Se Hun Choi, Kyeong Soon Kim, Young Hee Mun
  • Publication number: 20120282426
    Abstract: Provided are a resistance heated sapphire single crystal ingot grower, a method of manufacturing a resistance heated sapphire single crystal ingot, a sapphire single crystal ingot, and a sapphire wafer. The resistance heated sapphire single crystal ingot grower comprises according to an embodiment includes a chamber, a crucible included in the chamber and containing an alumina melt, and a resistance heating heater included inside the chamber and heating the crucible.
    Type: Application
    Filed: January 19, 2012
    Publication date: November 8, 2012
    Inventors: Do Won SONG, Young Hee Mun, Sang Hoon Lee, Seong Oh Jeong, Chang Youn Lee
  • Patent number: 7732352
    Abstract: By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. By performing the disclosed two-step rapid thermal process, the distribution of defects can be accurately controlled and an ideal device active zone can be formed up to a certain distance from the surfaces of the wafer. In addition, it is possible to maximize the internal gettering (IG) efficiency by enabling the oxygen precipitates and the bulk stacking faults to have constant densities in the depth direction in an internal region of the wafer, that is, the bulk region. In order to obtain the constant concentration profile of the oxygen precipitates and the bulk stacking faults in the bulk region, the wafer is subjected to the aforementioned two-step rapid thermal process in a predetermined mixed gas atmosphere.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: June 8, 2010
    Assignees: Hynix Semiconductor Inc., Siltron Inc.
    Inventors: Young Hee Mun, Kun Kim, Chung Geun Koh, Seung Ho Pyi
  • Patent number: 7242075
    Abstract: By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. By performing the disclosed two-step rapid thermal process, the distribution of defects can be accurately controlled and an ideal device active zone can be formed up to a certain distance from the surfaces of the wafer. In addition, it is possible to maximize the internal gettering (IG) efficiency by enabling the oxygen precipitates and the bulk stacking faults to have constant densities in the depth direction in an internal region of the wafer, that is, the bulk region. In order to obtain the constant concentration profile of the oxygen precipitates and the bulk stacking faults in the bulk region, the wafer is subjected to the aforementioned two-step rapid thermal process in a predetermined mixed gas atmosphere.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: July 10, 2007
    Assignees: Hynix Semiconductor Inc., Siltron Inc.
    Inventors: Young Hee Mun, Kun Kim, Chung Geun Koh, Seung Ho Pyi
  • Publication number: 20050054124
    Abstract: By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. By performing the disclosed two-step rapid thermal process, the distribution of defects can be accurately controlled and an ideal device active zone can be formed up to a certain distance from the surfaces of the wafer. In addition, it is possible to maximize the internal gettering (IG) efficiency by enabling the oxygen precipitates and the bulk stacking faults to have constant densities in the depth direction in an internal region of the wafer, that is, the bulk region. In order to obtain the constant concentration profile of the oxygen precipitates and the bulk stacking faults in the bulk region, the wafer is subjected to the aforementioned two-step rapid thermal process in a predetermined mixed gas atmosphere.
    Type: Application
    Filed: October 31, 2003
    Publication date: March 10, 2005
    Inventors: Young Hee Mun, Kun Kim, Chung Koh, Seung Pyi