Patents by Inventor Young Hee Seo

Young Hee Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120323
    Abstract: The present disclosure relates to an apparatus for fabricating a display panel including: an attachment member having a fixing portion in a pressurization direction to which a pressurization header is fixed, an attachment driving member configured to move the attachment member and the pressurization header in the pressurization direction or a detachment direction through a fixing frame of the attachment member, a first pressure sensing module between the pressurization header and the attachment member and configured to generate first pressure detection signals according to pressure applied to the pressurization header, a gradient setting module configured to set a gradient of the pressurization header based on magnitudes of the first pressure detection signals, and a gradient control module configured to adjust gradients of the pressurization header, the attachment member, and the fixing frame according to control of the gradient setting module.
    Type: Application
    Filed: September 6, 2023
    Publication date: April 11, 2024
    Inventors: Tae Hee LEE, Sung Kook PARK, Kyung Ho KIM, Young Seok SEO, Jae Gwang UM, Sang Hyun LEE, Hyung Suk HWANG
  • Publication number: 20240120214
    Abstract: An apparatus for fabricating a display panel, the apparatus including: a loading module configured to accommodate a large-area fabricating substrate, the loading module being configured to adjust an inclination of the large-area fabricating substrate from a rear surface of the large-area fabricating substrate and to press the large-area fabricating substrate; and an element transfer module configured to transfer a plurality of light emitting elements or an integrated circuit onto the large-area fabricating substrate and configured to bond and press a wafer on which the plurality of light emitting elements or the at least one integrated circuit is located onto the large-area fabricating substrate.
    Type: Application
    Filed: September 18, 2023
    Publication date: April 11, 2024
    Inventors: Tae Hee LEE, Kyung Ho KIM, Young Seok SEO, Joo Woan CHO, Byeong Hwa CHOI
  • Publication number: 20240120324
    Abstract: An apparatus for fabricating a display panel, including a film fixing module configured to fix a stretched film on which a plurality of light emitting elements are arranged, a film pressurizing module configured to pressurize the stretched film, a first thickness detection module configured to detect, at each pressurization step, a modulus of elasticity and a change in thickness of the stretched film that is pressurized and stretched by the film pressurizing module, a second thickness detection module configured to detect, at each pressurization step, a change in thickness of an adhesive applied in a front direction of the stretched film, an image detection module configured to photograph the plurality of light emitting elements arranged on the stretched film for each pressurization step and to detect a change in arrangement information of the light emitting elements, and a main processor configured to database feature change information.
    Type: Application
    Filed: September 6, 2023
    Publication date: April 11, 2024
    Inventors: Tae Hee LEE, Kyung Ho KIM, Young Seok SEO, Joo Woan CHO, Byeong Hwa CHO
  • Patent number: 7964461
    Abstract: The present invention is related to a method of forming an isolation layer in a semiconductor device and comprises the steps of forming a tunnel insulating layer and conductive layer patterns on an active area of a semiconductor substrate, the width of an upper portion of the conductive layer patterns being narrower than that of a lower portion; forming a trench between the conductive layer patterns on the semiconductor substrate; forming an insulating layer to fill a portion of the trench with the insulating layer; and performing an etching process to remove an overhang of the insulating layer formed at an upper edge of the conductive layer patterns. Here, the step of forming the insulating layer and the step of performing the etching process are repeatedly performed until a space between the conductive layer patterns and the trench are filled with the insulating layer.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: June 21, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Hee Seo
  • Publication number: 20080213969
    Abstract: The present invention is related to a method of forming an isolation layer in a semiconductor device and comprises the steps of forming a tunnel insulating layer and conductive layer patterns on an active area of a semiconductor substrate, the width of an upper portion of the conductive layer patterns being narrower than that of a lower portion; forming a trench between the conductive layer patterns on the semiconductor substrate; forming an insulating layer to fill a portion of the trench with the insulating layer; and performing an etching process to remove an overhang of the insulating layer formed at an upper edge of the conductive layer patterns. Here, the step of forming the insulating layer and the step of performing the etching process are repeatedly performed until a space between the conductive layer patterns and the trench are filled with the insulating layer.
    Type: Application
    Filed: December 26, 2007
    Publication date: September 4, 2008
    Inventor: YOUNG HEE SEO