Patents by Inventor Young-Ho Kwak
Young-Ho Kwak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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System and method for certifying genuine product and generating music chart for copyright protection
Patent number: 11216826Abstract: A method for certifying a genuine product and generating a music chart performed by a server may include: receiving a genuine product certification request from a terminal of a buyer who purchased an album; transmitting genuine product certification content for a genuine product certification procedure to the terminal in response to the genuine product certification request; receiving certification information input to the genuine product certification content; comparing the received certification information with information stored in a database built in advance to perform genuine product certification for the album; matching the certification information with the album when the album is certified as a genuine product, storing the matched certification information in the database, and transmitting a certification completion message to the terminal; and generating the music chart based on the certification information.Type: GrantFiled: August 29, 2019Date of Patent: January 4, 2022Assignee: HANTEOGLOBAL CO., LTD.Inventor: Young Ho Kwak -
Patent number: 10747697Abstract: A PCIe capable semiconductor device includes; ports respectively configured to transmit and receive data in a PCIe environment, and a PCIe controller configured to set a link between the PCIe capable semiconductor device and another PCIe capable semiconductor device. The link includes at least one lane implemented over at least one of the ports. The PCIe controller includes a link training and status state machine (LTSSM) configured to perform a first lane number negotiation according to a first ordering of the ports and a second lane number negotiation according to a second ordering of the ports different from the first ordering of the ports, and determine an optimized link width for the link according to the results of the first lane number negotiation and the second lane number negotiation.Type: GrantFiled: September 5, 2017Date of Patent: August 18, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Young Ho Kwak, Kwang Hee Choi
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System and Method for Certifying Genuine Product and Generating Music Chart for Copyright Protection
Publication number: 20200151737Abstract: A method for certifying a genuine product and generating a music chart performed by a server may include: receiving a genuine product certification request from a terminal of a buyer who purchased an album; transmitting genuine product certification content for a genuine product certification procedure to the terminal in response to the genuine product certification request; receiving certification information input to the genuine product certification content; comparing the received certification information with information stored in a database built in advance to perform genuine product certification for the album; matching the certification information with the album when the album is certified as a genuine product, storing the matched certification information in the database, and transmitting a certification completion message to the terminal; and generating the music chart based on the certification information.Type: ApplicationFiled: August 29, 2019Publication date: May 14, 2020Inventor: Young Ho KWAK -
Publication number: 20180095920Abstract: A PCIe capable semiconductor device includes; ports respectively configured to transmit and receive data in a PCIe environment, and a PCIe controller configured to set a link between the PCIe capable semiconductor device and another PCIe capable semiconductor device. The link includes at least one lane implemented over at least one of the ports. The PCIe controller includes a link training and status state machine (LTSSM) configured to perform a first lane number negotiation according to a first ordering of the ports and a second lane number negotiation according to a second ordering of the ports different from the first ordering of the ports, and determine an optimized link width for the link according to the results of the first lane number negotiation and the second lane number negotiation.Type: ApplicationFiled: September 5, 2017Publication date: April 5, 2018Inventors: YOUNG HO KWAK, KWANG HEE CHOI
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Patent number: 8451970Abstract: The present disclosure provides a variable delay circuit comprising a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal; a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit; a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal; and a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.Type: GrantFiled: February 25, 2011Date of Patent: May 28, 2013Assignee: Korea University Research and Business FoundationInventors: Chul Woo Kim, Young Ho Kwak
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Patent number: 8442178Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.Type: GrantFiled: June 3, 2011Date of Patent: May 14, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Chul-Woo Kim, Seok-Soo Yoon, Young-Ho Kwak, In-Ho Lee, Ki-Hong Kim
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Patent number: 8149030Abstract: A clock generator includes a controller, a digital phase locked loop (PLL) circuit, a charge pump phase locked loop (PLL) circuit and a divider. The controller generates a division factor and a first internal clock signal in response to a low-frequency reference clock signal and a multiplication factor. The digital PLL circuit generates a second internal clock signal in response to the reference clock signal, the division factor and the first internal clock signal. The charge pump PLL circuit generates a plurality of third internal clock signals by using the second internal clock signal. The divider generates a high-frequency clock signal in response to a phase selection signal, the division factor and the third internal clock signals.Type: GrantFiled: January 21, 2010Date of Patent: April 3, 2012Assignees: Samsung Electronics Co., Ltd., Korea University Research and Business FoundationInventors: Chul-woo Kim, Woo-seok Kim, Min-young Song, Jae-jin Park, Ji-hyun Kim, Young-ho Kwak
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Publication number: 20110228887Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.Type: ApplicationFiled: June 3, 2011Publication date: September 22, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chul-Woo KIM, Seok-Soo YOON, Young-Ho KWAK, In-Ho LEE, Ki-Hong KIM
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Publication number: 20110216864Abstract: The present disclosure provides a variable delay circuit comprising a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal; a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit; a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal; and a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.Type: ApplicationFiled: February 25, 2011Publication date: September 8, 2011Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATIONInventors: Chul Woo Kim, Young Ho Kwak
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Patent number: 7974375Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.Type: GrantFiled: August 23, 2007Date of Patent: July 5, 2011Assignees: Samsung Electronics Co., Ltd., Korea University Industrial & Academic Collaboration FoundationInventors: Chul-Woo Kim, Seok-Soo Yoon, Young-Ho Kwak, In-Ho Lee, Ki-Hong Kim
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Patent number: 7830184Abstract: A frequency multiplier is disclosed. A plurality of voltage regulators each regulate levels of voltages at first and second common nodes in response to a corresponding one of input signals from a voltage-controlled delay line. An input buffer charges the first node or discharges the second node in response to a feedback signal. An output buffer regulates a level of a voltage at an output node and outputs a frequency-multiplied clock signal and the feedback signal corresponding to the voltage level of the output node. A discharge circuit discharges the first node before a rising edge of each of the input signals from the voltage-controlled delay line is inputted. A charge circuit charges the second node before the rising edge of each of the input signals from the voltage-controlled delay line is inputted.Type: GrantFiled: July 27, 2005Date of Patent: November 9, 2010Assignee: Korea University Industry and Academy Cooperation FoundationInventors: Chul-Woo Kim, Jin-Han Kim, Seok-Ryung Yoon, Young-Ho Kwak, Seok-Soo Yoon
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Publication number: 20100244914Abstract: A clock generator includes a controller, a digital phase locked loop (PLL) circuit, a charge pump phase locked loop (PLL) circuit and a divider. The controller generates a division factor and a first internal clock signal in response to a low-frequency reference clock signal and a multiplication factor. The digital PLL circuit generates a second internal clock signal in response to the reference clock signal, the division factor and the first internal clock signal. The charge pump PLL circuit generates a plurality of third internal clock signals by using the second internal clock signal. The divider generates a high-frequency clock signal in response to a phase selection signal, the division factor and the third internal clock signals.Type: ApplicationFiled: January 21, 2010Publication date: September 30, 2010Inventors: Chul-woo Kim, Woo-seok Kim, Min-young Song, Jae-jin Park, Ji-hyun Kim, Young-ho Kwak
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Patent number: 7639086Abstract: A thermometer code generator includes n bit storing stages that are coupled to each other, where n is an integer greater than 1, and the n bit storing stages store a thermometer code, and are adapted to increase the stored thermometer code by 1 in synchronization with a clock signal when an up signal is active, to decrease the stored thermometer code by 1 in synchronization with the clock signal when a down signal is active, and to maintain the stored thermometer code in synchronization with the clock signal when both of the up signal and the down signal are inactive.Type: GrantFiled: August 23, 2007Date of Patent: December 29, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: In-Ho Lee, Seok-Soo Yoon, Young-Ho Kwak, Ki-Hong Kim, Chulwoo Kim
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Publication number: 20090189652Abstract: A frequency multiplier is disclosed. A plurality of voltage regulators each regulate levels of voltages at first and second common nodes in response to a corresponding one of input signals from a voltage-controlled delay line. An input buffer charges the first node or discharges the second node in response to a feedback signal. An output buffer regulates a level of a voltage at an output node and outputs a frequency-multiplied clock signal and the feedback signal corresponding to the voltage level of the output node. A discharge circuit discharges the first node before a rising edge of each of the input signals from the voltage-controlled delay line is inputted. A charge circuit charges the second node before the rising edge of each of the input signals from the voltage-controlled delay line is inputted.Type: ApplicationFiled: July 27, 2005Publication date: July 30, 2009Inventors: Chul-Woo Kim, Jin-Han Kim, Seok-Ryung Yoon, Young-Ho Kwak, Seok-Soo Yoon
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Publication number: 20080049884Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.Type: ApplicationFiled: August 23, 2007Publication date: February 28, 2008Applicants: Samsung Electronics Co., Ltd., Korea University Industrial & Academic Collaboration FoundationInventors: Chul-Woo KIM, Seok-Soo YOON, Young-Ho KWAK, In-Ho LEE, Ki-Hong KIM
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Publication number: 20080048904Abstract: A thermometer code generator includes n bit storing stages that are coupled to each other, where n is an integer greater than 1, and the n bit storing stages store a thermometer code, and are adapted to increase the stored thermometer code by 1 in synchronization with a clock signal when an up signal is active, to decrease the stored thermometer code by 1 in synchronization with the clock signal when a down signal is active, and to maintain the stored thermometer code in synchronization with the clock signal when both of the up signal and the down signal are inactive.Type: ApplicationFiled: August 23, 2007Publication date: February 28, 2008Inventors: In-Ho Lee, Seok-Soo Yoon, Young-Ho Kwak, Ki-Hong Kim, Chulwoo Kim