Abstract: A method of controlling a side push-pull (SPP) balance in a dual push-pull (DPP) type tracking servo employing both a main push-pull (MPP) balance and the SPP balance includes rotating a disc without performing a tracking servo, periodically shifting a pickup from a track center to the right and left by a first distance, obtaining an SPP signal and low-pass filtering the SPP signal to obtain a DC component, and adjusting an offset of the SPP signal so that the DC component of the SPP signal is 0. Since the pickup is forcibly and periodically shifted from the track center to the right and left by the predetermined distance during an SPP balance control, the SPP balance control can be effectively performed even on a disc having little eccentricity.

Abstract: Disclosed is a method for manufacturing a solid electrolytic capacitor using a functional polymer composition. The method comprises immersing the rolled aluminum electrolytic capacitor device in polyaniline solution with high electric conductivity to impregnate the device with polyaniline, drying the impregnated device in a drying oven which is maintained at constant temperature to fully remove the solvent, inserting the dried device to a capacitor aluminum can and then sealing with epoxy resin, to manufacture a solid electrolytic capacitor using a functional polymer. As such, the impregnation can be performed well at not only normal temperature and pressure, but also high temperature and reduced pressure. The solid electrolytic capacitor has the advantages of high capacity, low impedance and low ESR, and also, low manufacturing cost, simple processes and high reliability.

Abstract: Disclosed is a method for manufacturing a solid electrolytic capacitor using a functional polymer composition. The method comprises immersing the rolled aluminum electrolytic capacitor device in polyaniline solution with high electric conductivity to impregnate the device with polyaniline, drying the impregnated device in a drying oven which is maintained at constant temperature to fully remove the solvent, inserting the dried device to a capacitor aluminum can and then sealing with epoxy resin, to manufacture a solid electrolytic capacitor using a functional polymer. As such, the impregnation can be performed well at not only normal temperature and pressure, but also high temperature and reduced pressure. The solid electrolytic capacitor has the advantages of high capacity, low impedance and low ESR, and also, low manufacturing cost, simple processes and high reliability.

Abstract: MOSFET comprising:

Abstract: In a dual-damascene processes for multi level interconnection a method for forming trenches and vias in the inter-insulation is accomplished without etching out the inter-insulation layer. A thick sacrificial layer is first deposited and reversed etched to form sacrificial pillars 64 forming the vias and sacrificial bridges 72 forming the trenches. The sacrificial layer can be any material (insulator, semiconductor, or metal), provided it can be easily patterned and selectively removed later over the inter insulator layer. Thereafter a low-k inter-insulation layer is deposited around the sacrificial pillars and bridges. It is these sacrificial pillars and bridges that are etched away leaving behind vias and trenches in the inter-insulation layer. An advantage of the invention is that it replaces a difficult RIE process of vias and trenches with a much easier RIE of sacrificial pillars and bridges.

Abstract: The present invention relates to a recessed channel/gate MOSFET structure which comprises a semiconductor wafer having a plurality of shallow trench isolation regions embedded therein, wherein between each adjacent shallow trench isolation region is a field effect transistor region which comprises a source and drain region which are spaced apart by a gate region, said gate region comprising a poly gate region which is positioned between oxide spacers, said poly gate region having a metal contact region on its top surface and a gate oxide region on its bottom surface embedded in said semiconductor wafer and wherein said source and drain regions have an extension which wraps around said oxide spacers and provides a connection with a channel region which is formed below said gate oxide region.

Abstract: The present invention provides a process of fabricating high aspect ratio holes (H/L is 2 or greater) in a semiconductor structure wherein a masked gate-like reactive ion etch process is employed. The high aspect ratio holes have perfectly vertical sidewalls thus they are particularly useful in fabricating gate electrodes of sub-0.05 .mu.m MOSFETs using a damascene process.

Abstract: A method for etching silicon is described incorporating first and second steps of reactive ion etching through a patterned oxide layer in respective atmospheres of HBr, Cl.sub.2 and O.sub.2 and then HBr and O.sub.2 in situ by terminating the first etching step and removing substantially all Cl.sub.2 before continuing with the second step of etching. The invention overcomes the problem of uneven etching of n+ and p+ silicon gates for CMOS transistor logic during the step of simultaneously etching silicon to form sub 0.25 micron gate lengths and vertical sidewalls while stopping on the gate oxide.

Abstract: An improved bit sequential type parallel comparator capable of locating a minimum value among values of `m` bits stored in `n` registers within `m` clock cycles and the location thereof by bit-sequentially receiving those values, which includes a bit sequential type parallel comparator, which includes a minimum data detection circuit for detecting a minimum data by comparing a data of `m` bits sequentially inputted from `n` registers within `m` clock cycles; a minimum data generation circuit for generating a 1's complementary value of a minimum data using the data of `n` bits obtained by the minimum data detection circuit and an enable signal inputted from an eternally connected element; a minimum location information detection circuit for detecting a location of the minimum value among the `n` register values using the data obtained by the minimum data generation circuit and the data obtained by the minimum data detection circuit and for resetting the minimum data detection circuit upon location of the minim