Abstract: A semiconductor package includes: a substrate having an upper surface and a lower surface; an integrated circuit chip having bond pads; a lid attached on the upper surface of the substrate so as to cover the chip; and one or more projections that electrically connect the lid to a plurality of ground patterns. The substrate has substrate pads formed on the upper surface, and one or more of the substrate pads extend to form the ground patterns. The chip is bonded on the upper surface of the substrate. One or more of the bond pads are ground bond pads, and the bond pads are electrically connected to the corresponding substrate pads. An electrically nonconductive adhesive is used for the attachment of the lid to the substrate, and the projections are connected to the ground patterns by an electrically conductive adhesive. The ground projections are positioned at four corners of a cavity that is formed between the substrate and the lid.

Abstract: A semiconductor package includes: a substrate having an upper surface and a lower surface; an integrated circuit chip having bond pads; a lid attached on the upper surface of the substrate so as to cover the chip; and one or more projections that electrically connect the lid to a plurality of ground patterns. The substrate has substrate pads formed on the upper surface, and one or more of the substrate pads extend to form the ground patterns. The chip is bonded on the upper surface of the substrate. One or more of the bond pads are ground bond pads, and the bond pads are electrically connected to the corresponding substrate pads. An electrically nonconductive adhesive is used for the attachment of the lid to the substrate, and the projections are connected to the ground patterns by an electrically conductive adhesive. The ground projections are positioned at four corners of a cavity that is formed between the substrate and the lid.

Abstract: A semiconductor chip package comprising a chip with a lid having venting holes hermetically sealed with screws and a manufacturing method thereof are provided. The semiconductor chip package of the present invention comprises a chip such as a central processing unit (CPU) chip generating a large amount of heat; a substrate having upper and lower surfaces, the chip attached to the upper surface of the substrate; external connection terminals extending from the lower surface of the substrate and electrically connected to the chip; a lid attached to the upper surface of the substrate. The lid has a cavity for receiving the chip on a lower surface and venting holes penetrating the lid. The package includes sealing screws for hermetically sealing the venting holes. With the present invention, the venting holes formed through the lid are hermetically sealed without creating any voids or cracks in the sealant as in the prior art.