Patents by Inventor Young Hun JUN

Young Hun JUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD FOR FORMING SEMICONDUCTOR DIE AND SEMICONDUCTOR DEVICE THEREOF
    Publication number: 20240128123
    Abstract: A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 18, 2024
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Jin Won JEONG, Jang Hee LEE, Young Hun JUN, Jong Woon LEE, Jae Sik CHOI
  • Method for forming semiconductor die with die region and seal-ring region
    Patent number: 11887892
    Abstract: A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: January 30, 2024
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jin Won Jeong, Jang Hee Lee, Young Hun Jun, Jong Woon Lee, Jae Sik Choi
  • METHOD FOR FORMING SEMICONDUCTOR DIE AND SEMICONDUCTOR DEVICE THEREOF
    Publication number: 20220005733
    Abstract: A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.
    Type: Application
    Filed: April 15, 2021
    Publication date: January 6, 2022
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Jin Won JEONG, Jang Hee LEE, Young Hun JUN, Jong Woon LEE, Jae Sik CHOI