Abstract: Provided is a method for inhibiting extractant degradation in the DSX process through the metal extraction control, the method comprising steps of: (a) adding limestone to a copper solvent extraction-raffinate to precipitate iron (Fe) and aluminum (Al) as a slurry, recovering a clarifying liquid; and (b) adding sulfuric acid to the recovered clarifying liquid to adjust the pH thereof.

Abstract: Provided is an aerogel blanket and a method for producing the same, wherein a catalyzed sol I sufficiently and uniformly impregnated into a blanket in an impregnation tank, and the catalyzed sol is allowed to stay in the impregnation tank for a specific time to control fluidity while achieving a viscosity at which the catalyzed sol can be easily introduced into the blanket, thereby forming a uniform aerogel in the blanket. As a result, the uniformity of pore structure and thermal insulation performance of an aerogel blanket are improved, the loss of raw materials is reduced through the impregnation process, the occurrence of process problems is reduced, and the generation of dust is reduced.

Abstract: Disclosed herein is a method of preparing a silica aerogel. The silica aerogel is prepared by adding a first water glass solution and an acid catalyst to a reactor to form a first silica wet gel. The method further includes adding a second water glass solution and an acid catalyst to the first silica wet gel. The method further includes adding a surface modifier solution to the first silica wet gel to form a second silica wet gel. The method further includes drying a silica wet gel including the first silica wet gel and the second silica wet gel. The prepared silica aerogel has a tap density of 0.032 to 0.070 g/mL and a carbon content of 11.2 to 12.1 wt %.

Abstract: The present invention relates to a method of preparing ultra-pure silicon carbide in which a super-porous spherical silica aerogel is used as a silica raw material. By preparing the silica aerogel particles using low-cost water glass, a reaction area with respect to a carbon raw material is increased to enable low-temperature synthesis of silicon carbide, the size and shape of silicon carbide powder may be uniformly controlled to prepare ultra-pure silicon carbide, and economic efficiency and productivity of the silicon carbide synthesis may be improved. Thus, it is expected that the silicon carbide powder prepared by the preparation method of the present invention may be provided as an optimized raw material for the preparation of silicon carbide sintered body and single crystal (ingot).

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

Abstract: A semiconductor device is provided. The semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.

Abstract: A message sharing method includes: receiving image data captured via an imaging unit; receiving text input by a user via the input unit; analyzing, by a processor, the text and the image data and extracting a first object related to the user by using at least one of a result of analyzing the text, a result of analyzing the image data, and a sensed value obtained from a sensor unit; editing the image data to further include the extracted first object, and converting the edited image data to a thumbnail format; sharing the converted image data and the text with another user via a chat room.

Abstract: Provided is a non-transitory computer readable medium including computer readable instruction, which when executed by a computer processor cause the computer to read image data extracted from a moving image file stored in the storage medium, a frame rate of the image data, and speed control data of the image data, determine a reproduction speed of a first section of the moving image file by analyzing the speed control data, calculate a change rate of the first section based on the reproduction speed of the first section; and reproduce the moving image file by increasing a reproduction time or removing some of a plurality of frames included in the first section based on the calculated change rate.

Abstract: A semiconductor package according to an embodiment of the present invention includes: a heat sink board including an insulated board and a first metal layer formed on the insulated board; at least one semiconductor chip placed on the first metal layer; a plurality of lead frames connected to the semiconductor chips used to electrically connect the semiconductor chips to the outside; and a package housing partially covering the heat sink board, wherein both end parts of the insulated board are projected further than both end parts of the first metal layer.

Abstract: A semiconductor device is provided including a substrate, a first gate structure, a first contact plug and a power rail. The substrate includes first and second cell regions extending in a first direction, and a power rail region connected to each of opposite ends of the first and second cell regions in a second direction. The first gate structure extends in the second direction from a boundary area between the first and second cell regions to the power rail region. The first contact plug is formed on the power rail region, and contacts an upper surface of the first gate structure. The power rail extends in the first direction on the power rail region, and is electrically connected to the first contact plug. The power rail supplies a turn-off signal to the first gate structure through the first contact plug to electrically insulate the first and second cell regions.

Abstract: A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.

Abstract: A method of inhibiting degradation of an extractant by utilizing several auxiliary means in the DSX process: includes (a) preparing adjustment of the concentration of an extractant of a DSX solvent to a certain range; (b) extracting a metal contained in a pregnant leached solution by adjusting the ratio of the extractant and the diluent in the DSX solvent to a certain range; (c) measuring the pH of the aqueous phase solution by separating mixture into the aqueous phase solution and the organic phase solvent using a settler after step of extracting; (d) controlling the pH by adding soda ash (Na2CO3) so as to maintain the pH of the aqueous phase solution to be 3 to 7; and (e) scrubbing with scrubbing solution having a zinc concentration of 2 to 20 g/L by zinc sulfate (ZnSO4) to remove the manganese from the organic phase solvent containing the extracted metal.

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises sequentially stacking a lower sacrificial layer and an upper sacrificial layer on a substrate, patterning the upper sacrificial layer to form a first upper sacrificial pattern and a second upper sacrificial pattern, forming a first upper spacer and a second upper spacer on sidewalls of the first upper sacrificial pattern and a second upper sacrificial pattern, respectively, using the first and second upper spacers as an etching mask to pattern the lower sacrificial layer to form a plurality of lower sacrificial patterns, forming a plurality of lower spacers on sidewalls of the lower sacrificial patterns, and using the lower spacers as an etching mask to pattern the substrate. The first and second upper spacers are connected to each other.

Abstract: A SAW filter is a high-frequency filter including a common terminal, a transmission terminal and a reception terminal through which high-frequency signals are inputted and outputted. The SAW filter includes: a first filter circuit having a first frequency band as a pass band, and connected to the common terminal and the transmission terminal; a second filter circuit having a second frequency band different from the first frequency band as a pass band, and connected to the common terminal and the reception terminal; an antenna connected to the common terminal; and at least one inductor connected in series between the common terminal and the first filter circuit or the second filter circuit.

Abstract: Provided is a method for inhibiting extractant degradation in the DSX process through the metal extraction control, the method comprising steps of: (a) adding limestone to a copper solvent extraction-raffinate to precipitate iron (Fe) and aluminum (Al) as a slurry, recovering a clarifying liquid; and (b) adding sulfuric acid to the recovered clarifying liquid to adjust the pH thereof.

Abstract: Provided is a method for inhibiting extractant degradation comprising preparing step, extracting step and scrubbing step, the method including: (a) the preparing step of a DSX solvent by adjusting the extractant concentration of the DSX solvent to a specific range; (b) the extracting step of metal included in the feed solution by adjusting the ratio of the organic (solvent) and an aqueous (solution) as a feed solution; (c) the scrubbing step of adjusting the zinc concentration of the solution using zinc sulfate; and (d) stripping step.

Abstract: Disclosed is technology in that a clip structure formed of an inexpensive and light metallic material to easily performing soldering on a corresponding metal and to reduce costs of a semiconductor package and to reduce the weight of the semiconductor package. The composite clip structure bent at a predetermined angle and being in charge of electrical connection between components in a semiconductor package includes a main metal layer formed of a conductive material with a predetermined thickness, and a lower functional layer formed below the main metal layer and formed of a different type of metal from a metallic component of the main metal layer, wherein the lower functional layer is attached to the main metal layer to be integrated thereinto, and wherein the main metal layer is formed of a single metal containing a largest amount of aluminum (Al) or a metal mixture containing a largest amount of Al.

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, a buried conductive layer disposed adjacent to the active region on the substrate and extending in the first direction, a gate electrode intersecting the active region and extending in a second direction crossing the first direction, a source/drain layer disposed on the active region on one side of the gate electrode, a gate isolation pattern disposed on the buried conductive layer so as to be disposed adjacent to one end of the gate electrode, and extending in the first direction, and a contact plug disposed on the source/drain layer, electrically connected to the buried conductive layer, and in contact with the gate isolation pattern.

Abstract: A semiconductor package according to an embodiment of the present invention Includes: a lead frame comprising a pad and a lead spaced apart from the pad by a regular interval; a semiconductor chip adhered on the pad; and a clip structure electrically connecting the semiconductor chip and the lead, wherein an one end of the clip structure connected to the semiconductor chip inclines with respect to upper surfaces of chip pads of the semiconductor chip and is adhered to the upper surfaces of the chip pads of the semiconductor chip. A semiconductor package according to another embodiment of the present invention includes: a semiconductor chip comprising one or more chip pads; one or more leads electrically connected to the chip pads; and a sealing member covering the semiconductor chip, wherein an one end of the lead inclines with respect to one surface of the chip pad and is adhered to the chip pad and an other end of the lead is exposed to the outside of the sealing member.

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises sequentially stacking a lower sacrificial layer and an upper sacrificial layer on a substrate, patterning the upper sacrificial layer to form a first upper sacrificial pattern and a second upper sacrificial pattern, forming a first upper spacer and a second upper spacer on sidewalls of the first upper sacrificial pattern and a second upper sacrificial pattern, respectively, using the first and second upper spacers as an etching mask to pattern the lower sacrificial layer to form a plurality of lower sacrificial patterns, forming a plurality of lower spacers on sidewalls of the lower sacrificial patterns, and using the lower spacers as an etching mask to pattern the substrate. The first and second upper spacers are connected to each other.