Abstract: Disclosed is an interface system including a first neuron cluster that outputs a first neuron signal including a first neuron request and first neuron data by performing a first arithmetic operation, and a first interface circuit that stores the first neuron data and outputs a first response, in response to the first neuron request. The first neuron cluster outputs a second neuron signal including a second neuron request and second neuron data by performing a second arithmetic operation, in response to the first response. Before the first data is transmitted to a second neuron cluster different from the first neuron cluster, the first interface circuit outputs the first response in response to a fact that the first neuron data is stored.

Abstract: Provided is a spike neural network circuit including a synapse configured to generate an operation signal based on an input spike signal and a weight, and a neuron configured to generate an output spike signal using a comparator configured to compare a voltage of a membrane signal generated based on the operation signal with a voltage of a threshold signal, wherein the comparator includes a bias circuit configured to conditionally supply a bias current of the comparator depending on the membrane signal.

Abstract: Disclosed is a neuron circuit, which includes a first bias circuit that adds a bias current to an input current to generate a biased input current, a logarithm-based neuron calculation circuit that performs a logarithm calculation on an amount of current of the biased input current to generate an input logarithm value and generates a biased output voltage by performing a logarithm-based Hodgkin-Huxley model calculation based on the input logarithm value, and a second bias circuit that adds a bias voltage to the biased output voltage to generate an output voltage.

Abstract: A neuron circuit including a first internal circuit that receives a plurality of spike input signals, generates a first sum value by summing a plurality of synaptic weights corresponding to the plurality of spike input signals, and outputs a second sum value by adding a membrane potential value to the first sum value, a spike generating circuit that generates a spike output signal, a membrane potential generating circuit that generates the membrane potential value, a second internal circuit that counts a last spike time based on the spike output signal, and an online learning circuit that receives a last input time from the first internal circuit and performs LTP learning based on the last input time or receives the last spike time from the second internal circuit and performs LTD learning based on the last spike time.

Abstract: Disclosed is an electronic device that supports a neural network including a neuron array including neurons, a row address encoder that receives spike signals from neurons and outputs request signals in response to the received spike signals, and a row arbiter tree that receives request signals from the row address encoder and outputs response signals in response to the received request signals. The row arbiter tree includes a first arbiter that arbitrates first and second request signals among request signals, a first latch circuit that stores a state of the first arbiter, a second arbiter that arbitrates third and fourth request signals among request signals, a second latch circuit that stores a state of the second arbiter, and a third arbiter that delivers a response signal to the first and second arbiters based on information stored in the first and second latch circuits.

Abstract: Disclosed is an encoder including event layer outputs first and second event signals, weight layer applies first and second weights to the first and second event signals respectively, and provides the first event signal in which the first weight is applied and the second event signal in which the second weight is applied to first node, and first spike generation circuit generates first input spike signal of which firing period is changed based on voltage level of the first node. The voltage level of the first node is reduced continuously, increases for first voltage corresponding to the first weight in response to the first event signal activated, and increases for second voltage corresponding to the second weight in response to the second event signal activated.

Abstract: Disclosed are a spike neural network apparatus based on a multi-encoding and an operating method thereof. The method of operating a spike neural network (SNN) apparatus that performs a multi-encoding, includes receiving an input signal by an encoding module, performing a rate coding and a temporal coding on the received input signal by the encoding module, generating an SNN input signal based on the performance result of the rate coding and the temporal coding, and transmitting the generated SNN input signal to a neuromorphic chip that performs a spike neural network (SNN) operation.

Abstract: Provided is a system-on-chip. A central controller is configured to, in response to a request from a host, generate a first signal for requesting error information related to an error from a design of an IP. A local controller is configured to generate a second signal including the error information of the target IP if the request from the host is determined to be for the target IP based on the first signal.

Abstract: Disclosed is a network-on-chip including a first data converter that receives first image data and second image data from at least one image sensor and encodes one image data among the first image data and the second image data, into first data, based on whether the first image data is identical to the second image data and a second data converter that receives non-image data from at least one non-image sensor and encodes the received non-image data into second data. The network-on-chip outputs the first data and the second data to transmit the first data and the second data to an external server at a burst length.

Abstract: Disclosed are an electronic impedance tuning apparatus for measuring a load-pull of a mobile amplifier and an electronic impedance tuning method therefor. An electronic impedance tuning apparatus according to one embodiment of the present invention comprises: a coupler for transferring, to transmission lines respectively connected to a through port and a coupled port, an input voltage inputted to an input port; a magnitude part for controlling a change in the magnitude of the impedance through a change in length difference of the transmission lines; and a phase part for controlling a change in the phase of the impedance through an equal length change of the transmission lines.

Abstract: Disclosed are an electronic impedance tuning apparatus for measuring a load-pull of a mobile amplifier and an electronic impedance tuning method therefor. An electronic impedance tuning apparatus according to one embodiment of the present invention comprises: a coupler for transferring, to transmission lines respectively connected to a through port and a coupled port, an input voltage inputted to an input port; a magnitude part for controlling a change in the magnitude of the impedance through a change in length difference of the transmission lines; and a phase part for controlling a change in the phase of the impedance through an equal length change of the transmission lines.

Abstract: Provided is a spike neural network circuit including a synapse configured to generate an operation signal based on an input spike signal and a weight, and a neuron configured to generate an output spike signal using a comparator configured to compare a voltage of a membrane signal generated based on the operation signal with a voltage of a threshold signal, wherein the comparator includes a bias circuit configured to conditionally supply a bias current of the comparator depending on the membrane signal.

Abstract: Provided is a system-on-chip. A central controller is configured to, in response to a request from a host, generate a first signal for requesting error information related to an error from a design of an IP. A local controller is configured to generate a second signal including the error information of the target IP if the request from the host is determined to be for the target IP based on the first signal.

Abstract: Provided is an electronic circuit for implementing a generative adversarial neural network. The electronic circuit includes a spike converter, a spike image generator, a spike image converter, and an image discriminator. The spike converter generates a first signal including spike signals. The number of the spike signals is determined based on first data associated with second data within a reference time interval. The spike image generator generates a second signal including spike signals being selected based on a weight among the spike signals of the first signal. The image converter converts the spike signals of the second signal to generate third data being represented in an analog domain. The image discriminator provides the spike image generator with result data being associated with a difference between a value of the third data and a value of the second data. The image generator determines the weight based on the result data.

Abstract: Provided is a semiconductor device including a target circuit, a monitoring circuit, and a voltage controller. The target circuit includes a transistor. The monitoring circuit is configured to measure a temperature of the target circuit or measure a delay time between an input and an output of the target circuit. The voltage controller is configured to adjust a driving voltage for driving the target circuit or a back-bias voltage for adjusting a threshold voltage of the transistor by referring to at least one of the temperature and the delay time. As the temperature increases, the delay time decreases.

Abstract: Provided is an on-chip network device which basically operates in a packet switching network mode, establishes an exclusive communication path according to a request for a specific path, performs networking in a circuit switching network mode, and switches a network mode back to the packet switching network mode, when communication in the circuit switching network mode is terminated.

Abstract: Provided is a semiconductor device including a target circuit, a monitoring circuit, and a voltage controller. The target circuit includes a transistor. The monitoring circuit is configured to measure a temperature of the target circuit or measure a delay time between an input and an output of the target circuit. The voltage controller is configured to adjust a driving voltage for driving the target circuit or a back-bias voltage for adjusting a threshold voltage of the transistor by referring to at least one of the temperature and the delay time. As the temperature increases, the delay time decreases.

Abstract: Provided is an on-chip network device which basically operates in a packet switching network mode, establishes an exclusive communication path according to a request for a specific path, performs networking in a circuit switching network mode, and switches a network mode back to the packet switching network mode, when communication in the circuit switching network mode is terminated.

Abstract: A method and apparatus for providing graphic editors are disclosed. The apparatus includes a coordinate system setting unit, a windowing unit, a window definition unit, a window manager unit, a graphics object setting unit, and an event processing unit. The coordinate system setting unit sets a coordinate system as a real-world coordinate system. The windowing unit converts figures within a data structure into coordinates of a window coordinate system. The window definition unit defines a pair of one view region and a real physical window as one virtual canvas window. The window manager unit converts coordinates of the virtual canvas window into window coordinates. The graphics object setting unit sets graphics objects corresponding to the data structure of the figures. The event processing unit provides a graphic editor so that an event is processed using the graphics characteristics and the graphics objects.

Abstract: A switch block circuit in a field programmable gate array is provided. The switch block circuit includes a configuration memory unit including first group memories and second group memories and a switching unit including first group switching transistors and second group switching transistors. The switch block circuit further includes a selection unit for correspondingly connecting the second group memories with the second group switching transistors depending on an operation mode. The switch block is efficiently reconfigurable depending on the intended use, and configuration memories unused in a specific operation mode may be applied to other purposes.