Patents by Inventor Young I. Kwon

Young I. Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6251695
    Abstract: A method of packaging and testing integrated circuit dies includes coupling a first integrated circuit to the substrate; encapsulating the first integrated circuit; and then testing the first integrated circuit. If testing is successful, a second integrated circuit is coupled to the substrate. In addition, the method may include encapsulating the second integrated circuit so that the first and second integrated circuits are part of a single monolithic module, such as a multichip module. The second integrated circuit may also be tested after encapsulation. The present invention may also be practiced by encapsulating and testing lesser value die before encapsulating higher value die. This reduces the chance that a higher value die will be rendered unusable because one of the lower value dies attached to the substrate is subsequently found defective after the higher value die has been encapsulated and/or tested.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: June 26, 2001
    Assignee: S3 Graphics Co., Ltd.
    Inventor: Young I. Kwon
  • Patent number: 5497547
    Abstract: Method and apparatus for improving the cooling of a molded package assembly for one or more integrated-circuit dies, each of which is attached to a die-attach paddle portion of a lead frame. The improved package includes a molded-plastic package body which is formed around the lead frame and the attached integrated-circuit die. The package body has one or more through-holes formed through it for passage of air, where the air currents are drawn by convection or forced through the through-hole for cooling the integrated-circuit die attached the die-attach paddle. The die-attach paddle has a corresponding hole formed in it and the through-hole formed in the package body is located adjacent to the hole in the die-attach paddle to form a through-channel through the lead frame and the molded plastic body for convection cooling. The die-attach paddle is covered with molded plastic material so that the die-attach paddle is not exposed in the through-channel.
    Type: Grant
    Filed: April 6, 1994
    Date of Patent: March 12, 1996
    Assignee: VLSI Technology, Inc.
    Inventor: Young I. Kwon
  • Patent number: 5462624
    Abstract: Method and apparatus for connecting an I/O pad of an integrated circuit die to an electrical lead or contact on a lead frame that uses interposers formed directly on the die attach pad of the lead frame. Each interposer is formed by etching one or more grooves, preferably of depth no more than half the die attach pad thickness, in the die attach pad adjacent to the lead frame electrical lead(s). The exposed surfaces of the grooves and the die attach pad are coated with a layer of electrically insulating material, and the grooves are then filled with an electrically conducting material, such as conductive epoxy. An electrically conducting wire is then bonded between an I/O pad of an integrated circuit die and the electrically conducting material in the groove, and between the electrically conducting material and an electrical lead of a lead frame.
    Type: Grant
    Filed: April 26, 1994
    Date of Patent: October 31, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Young I. Kwon
  • Patent number: 5430250
    Abstract: Single, continuous bonding wires for an integrated-circuit die are supported in mid-span by a support ring which is snap-fit or adhesively bonded to a die-attach paddle of a leadframe. The support member includes a groove formed in its distal end for receiving an adhesive material, if necessary, for securing the bonding wires in position to prevent wire-wash and electrically shorting of the bonding wires when a plastic molding compound is formed around the die and leadframe. Alternatively the bonding wires are contained within notches formed in the distal end of the support ring. A lid placed over the support ring provides an enclosure for the integrated-circuit die. Stacking of support rings on each other and concentric support rings provide various optional arrangements for supporting bonding wires.
    Type: Grant
    Filed: April 8, 1994
    Date of Patent: July 4, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Young I. Kwon
  • Patent number: 5376756
    Abstract: Single, continuous bonding wires for an integrated-circuit die are supported in mid-span by a support ring which is snap-fit or adhesively bonded to a die-attach paddle of a leadframe. The support member includes a groove formed in its distal end for receiving an adhesive material, if necessary, for securing the bonding wires in position to prevent wire-wash and electrically shorting of the bonding wires when a plastic molding compound is formed around the die and leadframe. Alternatively the bonding wires are contained within notches formed in the distal end of the support ring. A lid placed over the support ring provides an enclosure for the integrated-circuit die. Stacking of support rings on each other and concentric support rings provide various optional arrangements for supporting bonding wires.
    Type: Grant
    Filed: December 20, 1991
    Date of Patent: December 27, 1994
    Assignee: VLSI Technology, Inc.
    Inventor: Young I. Kwon
  • Patent number: 5369550
    Abstract: Method and apparatus for improving the cooling of a molded package assembly for one or more integrated-circuit dies, each of which is attached to a die-attach paddle portion of a lead frame. The improved package includes a molded-plastic package body which is formed around the lead frame and the attached integrated-circuit die. The package body has one or more through-holes formed through it for passage of air, where the air currents are drawn by convection or forced through the through-hole for cooling the integrated-circuit die attached the die-attach paddle. The die-attach paddle has a corresponding hole formed in it and the through-hole formed in the package body is located adjacent to the hole in the die-attach paddle to form a through-channel through the lead frame and the molded plastic body for convection cooling. The die-attach paddle is covered with molded plastic material so that the die-attach paddle is not exposed in the through-channel.
    Type: Grant
    Filed: September 2, 1992
    Date of Patent: November 29, 1994
    Assignee: VLSI Technology, Inc.
    Inventor: Young I. Kwon
  • Patent number: 5365409
    Abstract: A package design configuration for an integrated-circuit die includes a leadframe having its bonding fingers connected to the periphery of an electrically-insulated, heat-conductive substrate, formed, for example, of a ceramic material. A number of electrically conductive traces, or bonding islands, serve as intermediate bonding locations for shorter bonding wires connecting bonding pads on the integrated-circuit die to the bonding fingers of the leadframe. The conductive traces serving as bonding islands are formed by deposition of thin-film material using semiconductor fabrication techniques or by deposition of thick-film material using printing techniques. Various shapes and configurations of the conductive traces are available, such as elongated rectangular patterns, or zigzag patterns. Alternatively, the electrically-insulated, heat-conductive ceramic substrate is attached to the die-attach pad of a conventional leadframe.
    Type: Grant
    Filed: June 4, 1993
    Date of Patent: November 15, 1994
    Assignee: VLSI Technology, Inc.
    Inventors: Young I. Kwon, Louis H. Liang
  • Patent number: 5332864
    Abstract: An integrated circuit package characterized by an interposer including a thin, flexible, planar insulator having a plurality of substantially radial traces provided on one side thereof. The other side of the insulator is attached to the die attach pad of a lead frame, and an integrated circuit die is attached within a die attach area of the assembly. A first set of wires couples bonding pads of the die to the traces, and a second set of wires couples the traces to bonding fingers of the lead frame. The bonding fingers, interposer, die, and both sets of wires are then encapsulated in plastic. The interposer can be advantageously manufactured in a tape automated bonding (TAB) process to provide a low cost, high performance, and versatile lead frame assembly.
    Type: Grant
    Filed: December 27, 1991
    Date of Patent: July 26, 1994
    Assignee: VLSI Technology, Inc.
    Inventors: Louis Liang, Sang S. Lee, Young I. Kwon
  • Patent number: 5317106
    Abstract: A corrector ring maintains the coplanarity of the tips of the leads of a quad flat pack QFP package during shipping and handling. A first snap-fit or adhesively-fixed ring member has an inner peripheral surface which engages the lower walls of the QFP package. The ring member also has an outer peripheral surface which engages the inner surfaces of the resilient leads of the QFP package. A second snap-fit adhesively-fixed ring member is held in place over the outer surfaces of the leads.
    Type: Grant
    Filed: October 13, 1991
    Date of Patent: May 31, 1994
    Assignee: VLSI Technology, Inc.
    Inventor: Young I. Kwon
  • Patent number: 5200809
    Abstract: A technique for packaging an integrated-circuit die in a conventional molded-plastic package exposes the lead frame to which the integrated-circuit die is attached so that heat-conducting columns can be directly attached to the leadframe through vias formed in the molded plastic package. The vias expose selected areas of the lead-frame to which are attached the thermally conductive columns, which extend to an exterior surface of the molded plastic package so that the lead-frame and the conductive columns provide a path for conduction of heat from the die to the exterior of the package.
    Type: Grant
    Filed: September 27, 1991
    Date of Patent: April 6, 1993
    Assignee: VLSI Technology, Inc.
    Inventor: Young I. Kwon
  • Patent number: 5146310
    Abstract: A thermally enhanced leadframe having heat conductive paths which thermally couple a die attach pad to thermal connection points spread out as far as possible from each other on the perimeter of the package. The area of the heat conductive path is maximized to occupy substantially all area in the package not occupied by the electrically conductive paths between the wire bond locations and the external connection points such as pins. This configuration maximizes the area of the printed circuit board which is heated thereby increasing thermal cooling efficiency. Further, the leadframe configuration maximizes the area of contact between the integrated circuit package and the heat conductive path thereby increasing the thermal conductivity between the device junctions on the integrated circuit die and the ambient through the material of the package itself.
    Type: Grant
    Filed: July 18, 1991
    Date of Patent: September 8, 1992
    Assignee: National Semiconductor Corp.
    Inventors: Jaime A. Bayan, Jeffrey C. Demmin, Mark L. DiOrio, Young I. Kwon