Abstract: A controller may include: a memory suitable for storing map data and unmap data; a counter suitable for counting a number of the unmap data stored in the memory; a setter suitable for setting offset values to each of the unmap data when the number of the unmap data is equal to or greater than a predetermined threshold value; and a compressor suitable for compressing the unmap data to have a predetermined compression length based on the offset values.

Abstract: An operating method of a memory system may include: searching for, in a memory, target map data corresponding to the read request; loading the target map data from a memory device when the target map data are not searched; compressing the loaded target map data using a predetermined compression ratio depending on an available capacity of the memory; caching the compressed target map data in the memory; parsing the compressed target map data; reading target user data corresponding to the read request from the memory device based on the parsed target map data; and outputting the read target user data.

Abstract: An operating method of a memory system may include: allocating target map data to a target slot, among a plurality of slots within a compression engine; compressing the target map data to a set size in the target slot; switching the state of the target slot to a second state, when the compression is completed; generating an interrupt signal and providing the interrupt signal to a processor, when the state of the target slot is switched to the second state; providing a release command for the target slot to the compression engine in response to the interrupt signal; and switching the state of the target slot to the first state in response to the release command.

Abstract: In a memory controller for controlling an operation of a memory device, the memory controller includes a map table buffer, a compressed map buffer, and a processor. The map table buffer stores map data received from the memory device. The compressed map buffer stores compressed map data generated by compressing the map data. The processor controls operations of the map table buffer and the compressed map buffer.

Abstract: A data storage apparatus includes a nonvolatile memory device including block groups, a random access memory including a sequential map table that stores a sequential map entry for consecutive sequential write logical addresses, among write addresses received from a host apparatus, greater than or equal to a predetermined threshold number, and a processor configured to determine whether or not first sequential write logical addresses are present among logical addresses corresponding to physical addresses for a first region of a first block group when a write operation for the first region of the first block group in response to a write request received from the host apparatus is completed, generate a first sequential map entry for the first sequential write logical addresses when the first sequential write logical addresses are present, and store the first sequential map entry in the sequential map table.

Abstract: A controller includes a queue manager suitable for queueing an operation command into a queue; a processor suitable for controlling a memory device to perform an operation in response to the operation command; and a memory interface suitable for interfacing the memory device and sequentially processing the queued operation command in a queued order of the queue, wherein the memory interface includes an abort handler suitable for generating a meta table indicating abort information of an operation corresponding to the operation command, and suitable for deleting, when an abort command corresponding to a target operation command is received from a host, the target operation command in the queued order where the target operation command is processed.

Abstract: A data storage apparatus includes a nonvolatile memory device, a command queue configured to queue one or more normal commands and an abort command, a data buffer configured to temporarily store write data which is to be transmitted from the host apparatus to the nonvolatile memory device and read data which is read out from the nonvolatile memory device and is to be transmitted to the host apparatus, an abort handler configured to perform abort handling with respect to a normal command corresponding to the abort command among the normal commands, and a processor configured to instruct the abort handler to perform the abort handling before the normal commands are transmitted to the nonvolatile memory device.

Abstract: Provided herein may be a memory system and a method of operating the memory system. The memory system may include: a semiconductor memory device to which an address mapping table including a plurality of map segments is stored; and a controller configured to load and store, during a read operation, one or more map segments selected from among the plurality of map segments. The controller may include: a compression engine configured to compress the one or more map segments and generate one or more compressed map segments and metadata corresponding thereto; a map data loading buffer configured to store the one or more compressed map segments and the metadata; and a processor configured to store the one or more compressed map segments to a random access memory (RAM) using the metadata.

Abstract: A data storage device includes: a non-volatile memory device, a random access memory and a processor. The non-volatile memory device stores a plurality of L2P entries related to a plurality of logical addresses. The random access memory stores a sequential flag table including sequential flags for a plurality of sequential segments. Each of the sequential flags are flags representing whether physical addresses corresponding to the logical addresses of the sequential segments are sequential or not. The processor identifies a sequential flag of a sequential segment related to read logical address information based on the sequential flag table. The processor reads at least one of the L2P entries, which are correspond to the read logical address information based on the sequential flag and loads the read L2P entry into the random access memory.

Abstract: A data storage device may include a non-volatile memory device storing an address mapping table including a plurality of map segments and a controller including a random-access memory. The controller loads a compressed or non-compressed first map segment into the random-access memory based on meta-information of the first map segment in response to a read request received from a host device. The meta-information is stored in a map segment meta-information table stored in the random-access memory and the meta-information represents whether the map segments are compressible or not.

Abstract: A memory system may include: a plurality of memory devices; a cache memory suitable for caching request information applied from a host and data corresponding to the request information; and a controller suitable for backing up the request information and the corresponding data of the cache memory and state information of the cache memory in a backup space when a reset request is provided from the host, performing a reset operation on the plurality of memory devices, the cache memory, and the controller in response to the reset request, and restoring the request information and the corresponding data from the backup space to the cache memory by referring to the state information during a booting operation after the reset operation.