Abstract: Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch. At least two of the latch output signals are activated at different time intervals.

Abstract: Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch.

Abstract: Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch. At least two of the latch output signals are activated at different time intervals.

Abstract: Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch.

Abstract: A driving method of a display device includes sequentially outputting a plurality of eye tuning signals, receiving a plurality of checking information obtained from a data driving circuit, wherein the checking information indicates whether the data driving circuit is operating in response to each of the plurality of eye tuning signals, and selecting one optimal eye tuning signal among the plurality of eye tuning signals operating the data driving circuit on the basis of the checking information. Image signals are output on the basis of condition information of the optimal eye tuning signal.

Abstract: A data driver includes a gamma unit, a digital-to-analog converter, and an output buffer. The gamma unit receives at least one reference voltage, and generates a first gamma reference voltage corresponding to a first sub-pixel and a second gamma reference voltage corresponding to a second sub-pixel using the received at least one reference voltage. The digital-to-analog converter receives the first and second gamma reference voltages from the gamma unit, and generates a first gamma data value corresponding to the first sub-pixel using the first gamma reference voltage and a second gamma data value corresponding to the second sub-pixel using the second gamma reference voltage. The output buffer outputs a first frame including the first gamma data value and a second frame including the second gamma data value. The output buffer outputs the first and second frames in a repeated manner for every predetermined number of frames.

Abstract: A data driver includes a first data voltage generator, a data converter and a second data voltage generator. The first data voltage generator is configured to generate a first data voltage based on first pixel data and configured to output the first data voltage to a first data line, the first pixel data being generated based on a first gamma curve. The data converter is configured to convert second pixel data to first converted pixel data, the second pixel data being generated based on the first gamma curve, the first converted pixel data being generated based on a second gamma curve different from the first gamma curve. The second data voltage generator is configured to generate a second data voltage based on the first converted pixel data and configured to output the second data voltage to a second data line.

Abstract: A display device including: a display panel displaying an image based on first and second frames; a timing controller outputting a plurality of image signals for each of the first and second frames and outputting a test signal during a reset section; and a source driving chip outputting a plurality of data voltages corresponding to the image signals or a test voltage corresponding to the test signal. The reset section is arranged after the first frame and before the second frame, and the source driving chip blocks the data voltage in the second frame from being output to driving lines having an arrival time period equal to or less than a reference time period during the reset section, the arrival time period representing the amount of time taken to arrive at the test voltage from an initial voltage.

Abstract: A controller for a display panel includes a detector, a timing controller, and a voltage generator. The detector detects a predetermined pattern in an image signal. The timing controller generates a control signal based on detection of the pattern. The voltage generator changes at least one driving voltage for a display panel from a first level to a second level based on the control signal. The predetermined pattern may correspond to at least one region having a predetermined arrangement of at least first and second gray scale values of pixels in an image corresponding to the image signal.

Abstract: A display device includes a display panel, a gate driver, a data driver, and a driving control unit. The display panel includes pixels connected to a corresponding one of gate lines and a corresponding one of data lines. The gate driver drives the gate lines. The data driver includes first pads and second pads. The first pads are connected to each of first data lines of the data lines, and the second pads are connected to each of second data lines of the data lines. The driving control unit provides control signals and a data signal to the data driver, and to control the gate driver. The data driver includes a digital-to-analog converter and a switching circuit. The digital-to-analog converter converts the data signal into analog signals. The switching circuit sequentially outputs the analog signals to the first pads during a test mode.

Abstract: A display device includes a first interconnection line, a first data driver, a second interconnection line, an electrostatic discharge (ESD) circuit, and a display panel. The first connection line transmits a data driving signal. The first data driver includes the first interconnection line and output a data signal based on the data driving signal. The second interconnection line passes through the first data driver and transmits a gate driving signal. The ESD) circuit in the first data driver and discharges static electricity transmitted through the second interconnection line. The first gate driver outputs a gate signal based on the gate driving signal transmitted through the second interconnection line. The display panel receives the data signal and the gate signal.

Abstract: A data driver includes a first data voltage generator, a data converter and a second data voltage generator. The first data voltage generator is configured to generate a first data voltage based on first pixel data and configured to output the first data voltage to a first data line, the first pixel data being generated based on a first gamma curve. The data converter is configured to convert second pixel data to first converted pixel data, the second pixel data being generated based on the first gamma curve, the first converted pixel data being generated based on a second gamma curve different from the first gamma curve. The second data voltage generator is configured to generate a second data voltage based on the first converted pixel data and configured to output the second data voltage to a second data line.

Abstract: A display panel driving apparatus includes an image pattern analyzing part, a clock signal generating part and a data driving part. The image pattern analyzing part is configured to analyze an image pattern of an image data. The clock signal generating part is configured to generating a clock signal having a different pulse width according to the image pattern of an image data. The data driving part is configured to drive a data line of a display panel in response to the clock signal. Thus, power consumption and heating of the data driving part may be decreased.

Abstract: A display device includes a signal controller. A data driver is connected to the signal controller. A memory unit is connected to the signal controller. The memory unit stores data driver characteristic information corresponding to a manufacturer identification (ID) of each of a plurality of data drivers. The data driver transmits a manufacturer ID to the signal controller. The signal controller reads, from the memory unit, data driver characteristic information corresponding to the manufacturer ID received from the data driver, and the signal controller generates image data and a control signal based on the read data driver characteristic information.

Abstract: A data driver includes a gamma unit, a digital-to-analog converter, and an output buffer. The gamma unit receives at least one reference voltage, and generates a first gamma reference voltage corresponding to a first sub-pixel and a second gamma reference voltage corresponding to a second sub-pixel using the received at least one reference voltage. The digital-to-analog converter receives the first and second gamma reference voltages from the gamma unit, and generates a first gamma data value corresponding to the first sub-pixel using the first gamma reference voltage and a second gamma data value corresponding to the second sub-pixel using the second gamma reference voltage. The output buffer outputs a first frame including the first gamma data value and a second frame including the second gamma data value. The output buffer outputs the first and second frames in a repeated manner for every predetermined number of frames.

Abstract: A driving method of a display device includes sequentially outputting a plurality of eye tuning signals, receiving a plurality of checking information obtained from a data driving circuit, wherein the checking information indicates whether the data driving circuit is operating in response to each of the plurality of eye tuning signals, and selecting one optimal eye tuning signal among the plurality of eye tuning signals operating the data driving circuit on the basis of the checking information. Image signals are output on the basis of condition information of the optimal eye tuning signal.

Abstract: Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch.

Abstract: A controller for a display panel includes a detector, a timing controller, and a voltage generator. The detector detects a predetermined pattern in an image signal. The timing controller generates a control signal based on detection of the pattern. The voltage generator changes at least one driving voltage for a display panel from a first level to a second level based on the control signal. The predetermined pattern may correspond to at least one region having a predetermined arrangement of at least first and second gray scale values of pixels in an image corresponding to the image signal.

Abstract: A display device includes a display panel, a gate driver, a data driver, and a driving control unit. The display panel includes pixels connected to a corresponding one of gate lines and a corresponding one of data lines. The gate driver drives the gate lines. The data driver includes first pads and second pads. The first pads are connected to each of first data lines of the data lines, and the second pads are connected to each of second data lines of the data lines. The driving control unit provides control signals and a data signal to the data driver, and to control the gate driver. The data driver includes a digital-to-analog converter and a switching circuit. The digital-to-analog converter converts the data signal into analog signals. The switching circuit sequentially outputs the analog signals to the first pads during a test mode.

Abstract: A gate driver includes a gate integrated circuit (“IC”) chip which receives at least two scanning start signals and at least four clock control signals, and outputs a plurality of gate-on voltages, where at least two clock control signals of the at least four clock control signals are generated based on one scanning start signal of the at least two scanning start signals, timings of the at least two scanning start signals are independent of each other, and timings of the at least two clock control signals based on the one scanning start signal are independent of each other.