Abstract: A thin film transistor display panel capable of minimizing a bezel and a manufacturing method thereof are provided. The thin film transistor display panel includes: a substrate; a plurality of gate lines and data lines that cross each other on the substrate; a thin film transistor connected to the gate line and the data line; a pixel electrode connected to the thin film transistor; and a plurality of gate voltage supply lines arranged in a parallel direction with the data lines and connected to the plurality of gate lines, respectively, in which one pixel area is defined by two adjacent gate lines and two adjacent data lines, two pixel electrodes are formed in one pixel area, and the gate voltage supply lines pass between the two pixel electrodes formed in the same pixel area.

Abstract: A three dimensional image display device includes a liquid crystal display panel assembly which includes a first pixel and a second pixel disposed adjacent to each other in a vertical direction. The first pixel comprises a first subpixel and a second subpixel disposed adjacent to each other in the vertical direction, and the second pixel includes a third subpixel and a fourth subpixel which are disposed adjacent to each other in the vertical direction. The first subpixel and the third subpixel, or the second subpixel and the fourth subpixel display black in a three dimensional (3D) display mode and display a normal image in a two dimensional (2D) display mode.

Abstract: A stereoscopic display device is disclosed. The stereoscopy display device includes pixels arranged in rows and columns. The pixels are divided into pixel groups, each including a plurality of adjacent rows. Interference prevention patterns may be located between the pixel groups. Phase delay layers are disposed on the interference prevention patterns and have different phases. At least one storage electrode line may extend between the pixels in a direction of the rows. The stereoscopic display device prevents interference between left and right-eye images and has high luminance.

Abstract: A thin film transistor display panel capable of minimizing a bezel and a manufacturing method thereof are provided. The thin film transistor display panel includes: a substrate; a plurality of gate lines and data lines that cross each other on the substrate; a thin film transistor connected to the gate line and the data line; a pixel electrode connected to the thin film transistor; and a plurality of gate voltage supply lines arranged in a parallel direction with the data lines and connected to the plurality of gate lines, respectively, in which one pixel area is defined by two adjacent gate lines and two adjacent data lines, two pixel electrodes are formed in one pixel area, and the gate voltage supply lines pass between the two pixel electrodes formed in the same pixel area.

Abstract: A three dimensional image display device includes a liquid crystal display panel assembly which includes a first pixel and a second pixel disposed adjacent to each other in a vertical direction. The first pixel comprises a first subpixel and a second subpixel disposed adjacent to each other in the vertical direction, and the second pixel includes a third subpixel and a fourth subpixel which are disposed adjacent to each other in the vertical direction. The first subpixel and the third subpixel, or the second subpixel and the fourth subpixel display black in a three dimensional (3D) display mode and display a normal image in a two dimensional (2D) display mode.

Abstract: A display device includes a first receiving container, a display panel, and a second receiving container. The first receiving container includes a receiving bottom portion and a receiving side portion. The receiving side portion extends from an edge of the receiving bottom portion. The receiving bottom portion and the receiving side portion together define a receiving space therein. The display panel is positioned in the first receiving container. The display panel is configured for displaying images. The second receiving container includes a panel support portion and a chassis side portion. The second receiving container is partially combined with the first receiving container. The panel support portion fixes an edge of the display panel. The chassis side portion extends from an edge of the panel support portion. The receiving container and the top chassis may be efficiently combined without aid of a screw.

Abstract: An LCD having a plurality of test pads applied with a common voltage, covered with respective shielding conductor or located sufficiently far from pixels. A gate wire including pluralities of gate lines and test pads disconnected from the gate lines and located near one ends of the gate lines, and a common electrode wire including a plurality of common electrodes and a common electrode pad connected to the common electrode electrodes are formed on a substrate, and covered with a gate insulating film. A data wire and a pixel electrode wire are formed thereon and covered with a passivation film. The passivation film and the gate insulating film have contact holes exposing the test pads and the common electrode pad. A plurality of connecting members which are connected to the test pads and the common electrode pad through the contact holes are formed on the passivation film.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 ??cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with An Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl(+He) or SF6+Cl2(+He) can form the edge profile of contact holes to be smoothed.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: An LCD having a plurality of test pads applied with a common voltage, covered with respective shielding conductor or located sufficiently far from pixels. A gate wire including pluralities of gate lines and test pads disconnected from the gate lines and located near one ends of the gate lines, and a common electrode wire including a plurality of common electrodes and a common electrode pad connected to the common electrode electrodes are formed on a substrate, and covered with a gate insulating film. A data wire and a pixel electrode wire are formed thereon and covered with a passivation film. The passivation film and the gate insulating film have contact holes exposing the test pads and the common electrode pad. A plurality of connecting members which are connected to the test pads and the common electrode pad through the contact holes are formed on the passivation film.

Abstract: The Mo or MoW composition layer has the low resistivity less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy etchant or a Cr etchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor device along with an Al layer and a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using a polymer layer, an etch gas system CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas SF6+HCl(+He) or SF6+Cl2(+He) can form the edge profile of contact holes to be smoothed.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.