Patents by Inventor Young-Jee Yoon

Young-Jee Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9892983
    Abstract: An apparatus and method of forming an epitaxial layer are provided. The apparatus includes a process chamber in which an epitaxial process is performed to form epitaxial layer on a substrate. A first supplier supplies source gases for the epitaxial layer into the process chamber. A second supplier supplies dopants into the process chamber. A detector detects a composition ratio of the epitaxial layer and a concentration of the dopants in the epitaxial layer during the epitaxial growth process. And a controller controls a mass flow of at least one of the source gases and a mass flow of the dopants in-line with the epitaxial growth process. Accordingly, the layer thickness of the epitaxial layer can be accurately controlled in real time in line with the epitaxial process.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Kook Kim, Bang-Won Kim, Yu-Sin Yang, Young-Jee Yoon, Sang-Kil Lee, Yoo-Seok Jang, Chung-Sam Jun
  • Publication number: 20160181167
    Abstract: An apparatus and method of forming an epitaxial layer are provided. The apparatus includes a process chamber in which an epitaxial process is performed to form epitaxial layer on a substrate. A first supplier supplies source gases for the epitaxial layer into the process chamber. A second supplier supplies dopants into the process chamber. A detector detects a composition ratio of the epitaxial layer and a concentration of the dopants in the epitaxial layer during the epitaxial growth process. And a controller controls a mass flow of at least one of the source gases and a mass flow of the dopants in-line with the epitaxial growth process. Accordingly, the layer thickness of the epitaxial layer can be accurately controlled in real time in line with the epitaxial process.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 23, 2016
    Inventors: Min-Kook KIM, Bang-Won KIM, Yu-Sin YANG, Young-Jee YOON, Sang-Kil LEE, Yoo-Seok JANG, Chung-Sam JUN
  • Patent number: 7747063
    Abstract: In an embodiment of a method of inspecting a substrate, the substrate on which minute structures are formed is divided into a plurality of inspection regions. A main inspection region among the inspection regions is selected. A main image of the main inspection region and sub-images of sub-inspection regions adjacent to the main inspection region are obtained. An average image of the main image and the sub-images is obtained. The average image is then compared with the main image to detect defects in the main inspection region. Gray levels may be used. The average image may have improved quality so that the defects in the selected inspection region may be rapidly and accurately detected. This process has an improved reliability. Further, the number of inspecting processes for the substrate may be reduced. And a line for the inspection process may be automated so that a worker-free line may be established.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: June 29, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Taek Lim, Chung-Sam Jun, Young-Jee Yoon, Sung-Hong Park
  • Patent number: 7697130
    Abstract: A surface inspection apparatus and method increase wafer productivity, wherein to increase an efficiency of the surface inspection apparatus to detect defects during a scanning of the wafer surface, a scanning speed for a subsequent defect detection is varied according to an increase/decrease of defect density represented on a plurality of images acquired successively. When the density of defects is reduced, the scanning speed increases and a level of a skip rule increases, and when the density of defects increases, the scanning speed decreases and a level of the skip rule decreases to precisely detect defects, thereby increasing reliability, throughput, and productivity.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: April 13, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Seok Ko, Yu-Sin Yang, Young-Jee Yoon, Chung-Sam Jun
  • Patent number: 7626164
    Abstract: In an embodiment, a method of scanning a substrate, and a method and an apparatus for analyzing crystal characteristics are disclosed. A sequential scan on the scan areas using a first electron beam and a second electron beam are repeatedly performed. The electrons accumulated in the scan areas by the first electron beam are removed from the scan areas by the second electron beam. When a size of the scan area is substantially the same as a spot size of the first electron beam, adjacent scan areas partially overlap each other. When each of the scan areas is larger than a spot size of the first electron beam, the adjacent scan areas do not overlap each other. Images of the scan areas are generated using back-scattered electrons emitted from each of the scan areas by irradiating the first electron beam to analyze crystal characteristics of circuit patterns on the substrate.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: December 1, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Jee Yoon, Jung-Taek Lim, Tae-Sung Kim, Chung-Sam Jun, Sung-Hong Park
  • Publication number: 20090219520
    Abstract: A surface inspection apparatus and method increase wafer productivity, wherein to increase an efficiency of the surface inspection apparatus to detect defects during a scanning of the wafer surface, a scanning speed for a subsequent defect detection is varied according to an increase/decrease of defect density represented on a plurality of images acquired successively. When the density of defects is reduced, the scanning speed increases and a level of a skip rule increases, and when the density of defects increases, the scanning speed decreases and a level of the skip rule decreases to precisely detect defects, thereby increasing reliability, throughput, and productivity.
    Type: Application
    Filed: February 9, 2009
    Publication date: September 3, 2009
    Inventors: Woo-Seok Ko, Yu-Sin Yang, Young-Jee Yoon, Chung-Sam Jun
  • Patent number: 7498248
    Abstract: In the methods of compensating for an alignment error during fabrication of structures on semiconductor substrates, a conductive pattern structure is formed at a first position on a first semiconductor substrate. The conductive pattern structure includes a grid of first and second conductive patterns arranged as columns and intersecting rows with openings bounded therebetween. A first conductive contact structure overlaps the conductive pattern structure, and includes a plurality of spaced apart conductive contacts arranged as a grid of rows and columns that can be tilted at a non-zero angle relative to the grid of the conductive pattern structure. A determination is made as to whether the first conductive contact structure is electrically connected to the conductive pattern structure.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: March 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Taek Lim, Dong-Chun Lee, Young-Jee Yoon, Sung-Hong Park
  • Publication number: 20070120054
    Abstract: In an embodiment, a method of scanning a substrate, and a method and an apparatus for analyzing crystal characteristics are disclosed. A sequential scan on the scan areas using a first electron beam and a second electron beam are repeatedly performed. The electrons accumulated in the scan areas by the first electron beam are removed from the scan areas by the second electron beam. When a size of the scan area is substantially the same as a spot size of the first electron beam, adjacent scan areas partially overlap each other. When each of the scan areas is larger than a spot size of the first electron beam, the adjacent scan areas do not overlap each other. Images of the scan areas are generated using back-scattered electrons emitted from each of the scan areas by irradiating the first electron beam to analyze crystal characteristics of circuit patterns on the substrate.
    Type: Application
    Filed: November 29, 2006
    Publication date: May 31, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Jee YOON, Jung-Taek LIM, Tae-Sung KIM, Chung-Sam JUN, Sung-Hong PARK
  • Publication number: 20070120220
    Abstract: In the methods of compensating for an alignment error during fabrication of structures on semiconductor substrates, a conductive pattern structure is formed at a first position on a first semiconductor substrate. The conductive pattern structure includes a grid of first and second conductive patterns arranged as columns and intersecting rows with openings bounded therebetween. A first conductive contact structure overlaps the conductive pattern structure, and includes a plurality of spaced apart conductive contacts arranged as a grid of rows and columns that can be tilted at a non-zero angle relative to the grid of the conductive pattern structure. A determination is made as to whether the first conductive contact structure is electrically connected to the conductive pattern structure.
    Type: Application
    Filed: October 31, 2006
    Publication date: May 31, 2007
    Inventors: Jung-Taek Lim, Dong-Chun Lee, Young-Jee Yoon, Sung-Hong Park
  • Publication number: 20070030479
    Abstract: In a method, with improved utilization of memory, of inspecting a defect on an object, the object is divided into a plurality of inspection regions. A plurality of levels is determined according to the numbers of defects, which are expected before detecting the defects, on the inspection regions. The defects on a selected inspection region are detected. The level including a range, which corresponds to the number of defects detected on the selected inspection region, is assigned to the selected inspection region with reference to the number of defects detected on the selected inspection region. The steps of detecting defects and assigning levels are repeated with respect to remaining inspection regions.
    Type: Application
    Filed: August 7, 2006
    Publication date: February 8, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Hong PARK, Young-Jee YOON, Jung-Taek LIM, Chung-Sam JUN
  • Publication number: 20070031025
    Abstract: In an embodiment of a method of inspecting a substrate, the substrate on which minute structures are formed is divided into a plurality of inspection regions. A main inspection region among the inspection regions is selected. A main image of the main inspection region and sub-images of sub-inspection regions adjacent to the main inspection region are obtained. An average image of the main image and the sub-images is obtained. The average image is then compared with the main image to detect defects in the main inspection region. Gray levels may be used. The average image may have improved quality so that the defects in the selected inspection region may be rapidly and accurately detected. This process has an improved reliability. Further, the number of inspecting processes for the substrate may be reduced. And a line for the inspection process may be automated so that a worker-free line may be established.
    Type: Application
    Filed: August 8, 2006
    Publication date: February 8, 2007
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-Taek Lim, Chung-Sam Jun, Young-Jee Yoon, Sung-Hong Park
  • Publication number: 20050191768
    Abstract: A substrate measuring apparatus includes a reference value storage unit, an electron irradiator, a current measuring device, and a property value calculating device. The reference value storage unit stores data on the relationship between current flow in a sample substrate with a contact hole of known characteristics that is irradiated by an electron beam. The current measuring device measures current flow in a test substrate. The property value calculating device calculates the property value of the contact hole formed in a material layer of the test substrate using the current flow in the test substrate and the data stored in the reference value storage unit. The property values of the contact hole may be a surface area of underlying substrate exposed by a contact hole or an amount of residual material remaining in the contact hole.
    Type: Application
    Filed: February 9, 2005
    Publication date: September 1, 2005
    Inventors: Young-Jee Yoon, Chung-Sam Jun, Chul-Gi Song, Sang-Mun Chon
  • Publication number: 20050151456
    Abstract: Electron-beam generators have wide area and directional beam generation capability. The generators include anode and cathode electrodes, which are disposed in spaced-apart and opposing relationship relative to each other. A clustered carbon nanotube array is provided to support the wide area and directional beam generation. The clustered nanotube array extends between the anode and cathode electrodes. The nanotube array also has a wide area emission surface thereon, which extends opposite a primary surface of the anode electrode. The clustered nanotube array is configured so that nanotubes therein provide conductive channels for electrons, which pass from the cathode electrode to the anode electrode via the emission surface.
    Type: Application
    Filed: January 4, 2005
    Publication date: July 14, 2005
    Inventors: Young-Jee Yoon, Chung-Sam Jun, Sang-Mun Chon