Abstract: The present invention relates to a method for preparing an inorganic compound using desulfurization gypsum for reducing greenhouse gas emissions, and, more specifically, to a method for preparing an inorganic compound, in which calcium sulfate and calcium carbonate, which have various uses as construction materials and the like, can be prepared using, as raw material, desulfurization gypsum which, being a recycled resource, is industrial waste, and an extraction agent, and the extraction agent can be reused after separation, and thus, compared to existing processes, greenhouse gases and manufacturing costs can be remarkably reduced.

Abstract: A power transfer system includes an electric vehicle supply equipment (EVSE) for providing electric power to an electric vehicle (EV) and an electric power reception device mounted in the EV; a first conductor plate electrically connected to a primary-side circuit of the EVSE; a compensation circuit for transferring a power input signal of the EVSE to the first conductor plate; a second conductor plate disposed in the EV and connected to the electric power reception device; and a secondary-side circuit for transferring a power signal received by the second conductor plate to a load, where the electric power is transferred from the EVSE to the EV by capacitive coupling between the first conductor plate and the second conductor plate.

Abstract: Provided in a semiconductor device including a substrate, an active region upwardly protruding from the substrate, a plurality of active fins upwardly protruding from the active region and extending in a first direction parallel to an upper surface of the substrate, the plurality of active fins being provided in a second direction that is parallel to the upper surface of the substrate and intersects with the first direction, and an isolation structure provided on the substrate, the isolation structure covering a sidewall of the active region and a lower portion of a sidewall of each of the plurality of active fins, wherein a first sidewall of the active region adjacent to a first active fin among the plurality of active fins has a staircase shape, the first active fin being provided on a first edge of the active region in the second direction.

Abstract: An SOC includes a security processor. The security processor includes an encryption/ECC encoding processor configured to perform an encryption operation on data using Metadata and to generate ECC data by performing ECC encoding processing on encrypted data and the Metadata, a decryption/ECC decoding processor configured to extract the encrypted data and the Metadata by performing ECC decoding processing using the ECC data and to recover the data by performing a decryption operation on the encrypted data using the Metadata, and an address controller configured to receive a first address related to storage of the data, to generate a second address based on the first address, and to perform an address generating operation identifying a same region in memory for storing the Metadata and the ECC data based on the second address.

Abstract: A security device includes a secure processor, a mail box, a cryptographic intellectual property (IP), a secure direct memory access (DMA) circuit, and an internal memory. The secure processor provides an isolated execution environment. The mail box transfers a request from a CPU to the secure processor. The cryptographic IP performs one or more secure operations, including a signature certification operation, an encryption/decryption operation, and an integrity verification operation, on secure data within the isolated execution environment and without intervention of the CPU. The secure DMA circuit controls the one or more secure operations within the isolated execution environment, wherein only the secure processor is configured to control the secure DMA circuit. The internal memory stores the secure data on which the one or more secure operations are performed. The cryptographic IP includes a DMA circuit configured to control data access to an external storage.

Abstract: An SOC includes a security processor. The security processor includes an encryption/ECC encoding processor configured to perform an encryption operation on data using Metadata and to generate ECC data by performing ECC encoding processing on encrypted data and the Metadata, a decryption/ECC decoding processor configured to extract the encrypted data and the Metadata by performing ECC decoding processing using the ECC data and to recover the data by performing a decryption operation on the encrypted data using the Metadata, and an address controller configured to receive a first address related to storage of the data, to generate a second address based on the first address, and to perform an address generating operation identifying a same region in memory for storing the Metadata and the ECC data based on the second address.

Abstract: A security device includes a secure processor, a mail box, a cryptographic intellectual property (IP), a secure direct memory access (DMA) circuit, and an internal memory. The secure processor provides an isolated execution environment. The mail box transfers a request from a CPU to the secure processor. The cryptographic IP performs one or more secure operations, including a signature certification operation, an encryption/decryption operation, and an integrity verification operation, on secure data within the isolated execution environment and without intervention of the CPU. The secure DMA circuit controls the one or more secure operations within the isolated execution environment, wherein only the secure processor is configured to control the secure DMA circuit. The internal memory stores the secure data on which the one or more secure operations are performed. The cryptographic IP includes a DMA circuit configured to control data access to an external storage.

Abstract: A cache memory includes a write-back determination unit and a burst length determination unit. The write-back determination unit determines whether a block is a write-back block based on an n-bit dirty value of the block. The burst length determination unit determines a burst length of write-back data included in the write-back block based on the n-bit dirty value and an minimum burst length, when the block is the write-back block.

Abstract: A cache memory includes a write-back determination unit and a burst length determination unit. The write-back determination unit determines whether a block is a write-back block based on an n-bit dirty value of the block. The burst length determination unit determines a burst length of write-back data included in the write-back block based on the n-bit dirty value and an minimum burst length, when the block is the write-back block.

Abstract: A cache memory includes a write-back determination unit and a burst length determination unit. The write-back determination unit determines whether a block is a write-back block based on an n-bit dirty value of the block. The burst length determination unit determines a burst length of write-back data included in the write-back block based on the n-bit dirty value and an minimum burst length, when the block is the write-back block. J:\SAM\1309\subspecredline.

Abstract: A cache memory unit includes: a cache memory; an early write-back condition checking unit for checking whether an early write-back condition has been satisfied; and an early write-back execution unit for monitoring a memory bus connecting the cache memory unit and an external memory unit, and in response to the memory bus being idle and the early write-back condition being satisfied, for causing dirty data in the cache memory to be written back to the external memory unit using the memory bus.

Abstract: Digital logic processing devices capable of reduced power consumption may be provided. A digital logic processing device may include one or more processing elements, an input FIFO for storing data, a processing unit, and a clock controller circuit. The processing unit may process data from the input FIFO and the clock controller circuit may control a clock signal supplied to the input FIFO and the processing unit. The clock controller circuit may monitor whether there is data to be transferred to the input FIFO and states of the input FIFO and the processing unit and may control the clock signal.

Abstract: A memory controller having graphic processing function that includes a graphic processing unit operating in response to a selection signal from a master, and a memory interface for storing outputs of the graphic processing unit in an external memory at and receiving graphic data from the external memory to provide the graphic data to the graphic processing unit.

Abstract: In systems and methods for graphic reproduction of an image including textural information, multiple rows or blocks of texture data can be retrieved from system memory in response to the single read command. In this manner, efficient use of system bus is achieved, and an increase in the texture cache hit ratio is realized, leading to more efficient system operation, and reduced system bus usage for texture data retrieval.

Abstract: An apparatus according to an example embodiment of the present invention, may process data of a present span. During processing, data corresponding to an address of the start data of the next span may be prefetched from the external memory device based on information related to the presently processed data. The prefetched data may store in the cache memory.

Abstract: A cache memory unit includes: a cache memory; an early write-back condition checking unit for checking whether an early write-back condition has been satisfied; and an early write-back execution unit for monitoring a memory bus connecting the cache memory unit and an external memory unit, and in response to the memory bus being idle and the early write-back condition being satisfied, for causing dirty data in the cache memory to be written back to the external memory unit using the memory bus.

Abstract: A cache memory includes a write-back determination unit and a burst length determination unit. The write-back determination unit determines whether a block is a write-back block based on an n-bit dirty value of the block. The burst length determination unit determines a burst length of write-back data included in the write-back block based on the n-bit dirty value and an minimum burst length, when the block is the write-back block.

Abstract: A three-dimensional (3D) graphic accelerator accessing an external memory storing a plurality of texture data is provided. The 3D graphic accelerator may include a texture cache storing the texture data, a geometry processing unit generating texture status information, and a texture processing unit generating a texture address to access the texture cache and outputting one or more texels from the texture data of the texture cache. The texture cache receives the texture address from the texture processing unit and generates a control signal for reading a part or all of a series of texture data from the external memory in accordance with the texture status information when a cache miss occurs.

Abstract: Provided are a memory controller for controlling a refresh cycle of a memory and a method thereof. In this method, a temperature measure command is generated to measure an operating temperature of the memory. Next, a measured temperature in response to the temperature measure command is received. Then, a temperature difference between the measured temperature and a reference temperature is detected if the measured temperature is different from the reference temperature to change the refresh cycle according to the temperature difference, and if the measured temperature is equal to the reference temperature the method returns to the temperature measure command generating step. Thereafter, a refresh command is applied to the memory in response to the changed refresh cycle.

Abstract: An apparatus for processing computer graphics data includes a perfragment unit performing a depth test with respect to a present fragment of graphics data, and a cache controller that prefetches a color value of the present fragment from an external memory device to a cache memory while the perfragment unit performs the depth test of the present fragment.