Patents by Inventor Young-Jin KO

Young-Jin KO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200411460
    Abstract: A semiconductor package includes a frame having a wiring structure and having a recess portion, a semiconductor chip having an active surface with a connection pad disposed thereon and disposed in the recess portion, an encapsulant sealing the semiconductor chip, and a redistribution layer having a first via connected to the connection and a second via connected to a portion of the wiring structure. The semiconductor chip includes a protective insulating film disposed on the active surface and having an opening exposing a region of the connection pad, and a redistribution capping layer connected to the region of the connection pad and extending onto the protective insulating film, and a surface of the redistribution capping layer is substantially the same level as a surface of the portion of the wiring structure, exposed from the first surface.
    Type: Application
    Filed: August 28, 2019
    Publication date: December 31, 2020
    Inventors: Yong Jin PARK, Sang Kyu LEE, Moon Il KIM, Myung Sam KANG, Jeong Ho LEE, Young Gwan KO
  • Publication number: 20200377915
    Abstract: Disclosed are recombinant strain of a genus Corynebacterium capable of producing biliverdin IX-alpha (IX?) and a method of producing biliverdin IX-alpha using the same. The recombinant strain is capable of synthesizing biliverdin IX-alpha in an environmentally friendly manner using only glucose without the addition of any nitrogen source, thus replacing the synthesis of biliverdin IX-alpha through chemical treatment, which is a conventional synthetic method causing environmental pollution problems.
    Type: Application
    Filed: April 15, 2020
    Publication date: December 3, 2020
    Applicant: Korea University Research and Business Foundation
    Inventors: Sung Ok HAN, Jiho SEOK, Young-jin KO
  • Patent number: 10844286
    Abstract: The present invention relates to a method for producing an impregnated pitch from a petroleum-based raw material and to an impregnated pitch produced using the same, and when the method for producing an impregnated pitch according to the present invention is used, it is possible to produce an impregnated pitch having a high carbonization yield (40 wt % or more) and low quinoline insoluble matter (QI, 2% or less) for improving efficiency of an impregnation process from a petroleum-based raw material. Therefore, when an impregnation process is applied to a carbon compact by using the impregnated pitch according to the present invention, it is possible to remarkably reduce micropores inside the carbon compact, and to produce a carbon compact having physical properties such as excellent electrical conductivity and mechanical strength.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: November 24, 2020
    Assignee: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY
    Inventors: Jong Gu Kim, Young-Pyo Jeon, Ji Sun Im, Byung Jin Song, Byong Chol Bai, Seung Hyun Ko, Jong Eun Choi
  • Publication number: 20200365657
    Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include: row lines; column lines intersecting the row lines; memory cells located in intersection regions of the row lines and the column lines, the memory cells including upper and lower electrodes; and interface layers located between the lower electrodes of the memory cells and the row lines, the interface layers having a width narrower than that of the row lines.
    Type: Application
    Filed: October 31, 2019
    Publication date: November 19, 2020
    Applicants: SK hynix Inc., SK hynix Inc.
    Inventors: Hyun Jin LEE, Young Seok KO, Jung Hun LEE, Hyun Min LEE
  • Patent number: 10818604
    Abstract: A semiconductor package includes a semiconductor chip having connection pads on one surface thereof, a first encapsulant covering at least portions of the semiconductor chip, and a connection structure disposed on the one surface of the semiconductor chip and including one or more redistribution layers electrically connected to the connection pads. A wiring structure is disposed on one surface of the first encapsulant opposing another surface of the first encapsulant facing towards the connection structure. The wiring structure has a passive component embedded therein, and includes one or more wiring layers electrically connected to the passive component. The one or more redistribution layers and the one or more wiring layers are electrically connected to each other.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myung Sam Kang, Yong Jin Park, Young Gwan Ko, Moon Il Kim
  • Publication number: 20200321398
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory comprises a first variable resistance element coupled between a first wiring and a second wiring, the first variable resistance element including a first variable resistance layer having a first width at a first distance from the first wiring; and a second variable resistance element coupled between the second wiring and a third wiring, the second variable resistance element including a second variable resistance layer having a second width at the first distance from the second wiring. The first width is greater than the second width.
    Type: Application
    Filed: September 16, 2019
    Publication date: October 8, 2020
    Inventors: Young-Seok KO, Jung-Hun LEE, Hyun-Min LEE, Hyun-Jin LEE
  • Publication number: 20200303314
    Abstract: A semiconductor package includes a semiconductor chip having connection pads on one surface thereof, a first encapsulant covering at least portions of the semiconductor chip, and a connection structure disposed on the one surface of the semiconductor chip and including one or more redistribution layers electrically connected to the connection pads. A wiring structure is disposed on one surface of the first encapsulant opposing another surface of the first encapsulant facing towards the connection structure. The wiring structure has a passive component embedded therein, and includes one or more wiring layers electrically connected to the passive component. The one or more redistribution layers and the one or more wiring layers are electrically connected to each other.
    Type: Application
    Filed: May 16, 2019
    Publication date: September 24, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myung Sam KANG, Yong Jin PARK, Young Gwan KO, Moon II KIM
  • Publication number: 20200291379
    Abstract: The present invention relates to an enzym complex in which a heme polymerase and a heme ligase are linked to each other via the dockerin module of cellulas, and to a method for producing a hemozoin using the same. The enzyme complex according to the present invention can polymerize heme with higher efficiency than conventional enzymes, and thus can more efficiently produce hemozoin, a conductive biopolymer.
    Type: Application
    Filed: December 6, 2017
    Publication date: September 17, 2020
    Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Sung Ok HAN, Jeong-Eun HYEON, Young-jin KO
  • Publication number: 20200270658
    Abstract: The present invention relates to a recombinant microorganism having an enhanced ability to produce heme, coproporphyrin III (Copro III), and uroporphyrin III (Uro III), and a method for producing heme, coproporphyrin III, and uroporphyrin III using same. When using a recombinant microorganism incorporating a gene that codes glutamyl-tRNA reductase (HemA), glutamate-1-semialdehyde aminotransferase (HemL), and diphtheria toxin repressor (DtxR), which is a transcription factor capable of inducing the expression of genes related to heme metabolic pathways, porphyrin-based structures can be produced at high yield, and thus the method is economic.
    Type: Application
    Filed: May 18, 2018
    Publication date: August 27, 2020
    Applicant: Korea University Research and Business Foundation
    Inventors: Sung Ok HAN, Young-jin KO
  • Publication number: 20200257840
    Abstract: A device for verifying a circuit design including a first circuit block and a second circuit block includes a verification vector generator and a design verifier. The verification vector generator determines a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block. The design verifier performs design verification for the first circuit block by using the first verification vector.
    Type: Application
    Filed: February 12, 2020
    Publication date: August 13, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In HUH, Jeong-hoon KO, Hyo-jin CHOI, Seung-ju KIM, Chang-wook JEONG, Joon-wan CHAI, Kwang-il PARK, Youn-sik PARK, Hyun-sun PARK, Young-min OH, Jun-haeng LEE, Tae-ho LEE
  • Publication number: 20200220039
    Abstract: Provided are a method of manufacturing a solar cell, including a polycrystalline silicon layer forming operation of forming a polycrystalline silicon layer containing a first dopant on a back surface of a semiconductor substrate formed of a single crystal silicon material including a base region, a front texturing operation of texturing a front surface of the semiconductor substrate and simultaneously removing the polycrystalline silicon layer formed on the front surface of the semiconductor substrate, a second conductive region forming operation of forming a second conductive region by diffusing a second dopant on the front surface of the semiconductor substrate, a passivation layer forming operation of forming a first passivation layer on the polycrystalline silicon layer formed on the back surface of the semiconductor substrate and forming a second passivation layer on the second conductive region of the front surface of the semiconductor substrate, and an electrode forming operation of forming a first ele
    Type: Application
    Filed: January 8, 2020
    Publication date: July 9, 2020
    Applicant: LG ELECTRONICS INC.
    Inventors: Won Jae Chang, Young Gu Do, Sung Jin Kim, Ju Hwa Cheong, Jun Yong Ahn, Hae Jong Cho, Ji Soo Ko
  • Patent number: 10697073
    Abstract: A method for manufacturing an electrode for hydrogen production using a tungsten carbide nanoflake may include: forming a tungsten carbide nanoflake on a nanocrystalline diamond film by means of a chemical vapor deposition process in which hydrogen plasma is applied; and increasing activity of the tungsten carbide nanoflake to a hydrogen evolution reaction by removing an oxide layer or a graphene layer from a surface of the tungsten carbide nanoflake. Since an oxide layer and/or a graphene layer of a surface of tungsten carbide is removed by means of cyclic cleaning after tungsten carbide is formed, hydrogen evolution reaction (HER) activity of the tungsten carbide may be increased, thereby enhancing utilization as a catalyst electrode.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: June 30, 2020
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Wook Seong Lee, Young-Jin Ko, Young Joon Baik, Jong-Keuk Park, Kyeong Seok Lee, Inho Kim, Doo Seok Jeong
  • Publication number: 20200144235
    Abstract: A semiconductor package includes a connection structure including an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer, a frame disposed on the connection structure and having a through-hole, a semiconductor chip disposed in the through-hole on the connection structure and having a connection pad disposed to face the connection structure, and a passive component disposed on the frame.
    Type: Application
    Filed: May 21, 2019
    Publication date: May 7, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myung Sam Kang, Young Gwan Ko, Yong Jin Park, Seon Hee Moon
  • Publication number: 20200123448
    Abstract: The present invention relates to a method for producing an impregnated pitch from a petroleum-based raw material and to an impregnated pitch produced using the same, and when the method for producing an impregnated pitch according to the present invention is used, it is possible to produce an impregnated pitch having a high carbonization yield (40 wt % or more) and low quinoline insoluble matter (QI, 2% or less) for improving efficiency of an impregnation process from a petroleum-based raw material. Therefore, when an impregnation process is applied to a carbon compact by using the impregnated pitch according to the present invention, it is possible to remarkably reduce micropores inside the carbon compact, and to produce a carbon compact having physical properties such as excellent electrical conductivity and mechanical strength.
    Type: Application
    Filed: December 26, 2017
    Publication date: April 23, 2020
    Inventors: Jong Gu Kim, Young-Pyo Jeon, Ji Sun Im, Byung Jin Song, Byong Chol Bai, Seung Hyun Ko, Jong Eun Choi
  • Patent number: 10541221
    Abstract: A fan-out semiconductor package includes a core member having a through-hole in which a semiconductor chip is disposed. The semiconductor chip has an active surface having connection pads disposed thereon and an inactive surface opposing the active surface. An encapsulant encapsulates at least a portion of the semiconductor chip. A connection member is disposed on the active surface of the semiconductor chip and includes a redistribution layer electrically connected to the connection pads of the semiconductor chip. A passivation layer is disposed on the connection member. The fan-out semiconductor package further has a slot spaced part from the through-hole and penetrating through at least a portion of the core member or the passivation layer.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: January 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Jin Seol, Myung Sam Kang, Young Gwan Ko
  • Publication number: 20200002803
    Abstract: Provided is a multilayer zinc alloy plated steel material comprising a base steel material and multiple plating layers formed on the base steel material, wherein each of the multiple plating layers includes one of a Zn plating layer, a Mg plating layer, and a Zn—Mg alloy plating layer, and the ratio of the weight of Mg contained in the multiple plating layers to the total weight of the multiple plating layers is from 0.13 to 0.24.
    Type: Application
    Filed: December 22, 2017
    Publication date: January 2, 2020
    Inventors: Young-Jin KWAK, Goo-Hwa KIM, Mun-Jong EOM, Seok-Jun HONG, Kyoung-Pil KO, Yong-Hwa JUNG, Dong-Yoeul LEE, Tae-Yeob KIM, Kyung-Hoon NAM
  • Publication number: 20190273308
    Abstract: According to various embodiments of the present disclosure, an electronic device may include: an array antenna including a plurality of first radiating conductors that transmit or receive a wireless signal in a first frequency band and are arranged on a circuit board; and a lens unit including at least one lens disposed on a housing of the electronic device to correspond to the first radiating conductors. The lens unit may refract or reflect a wireless signal transmitted/received through each of the first radiating conductors. The electronic device as described above may be variously implemented according to embodiments. For example, a portion of the lens unit may transmit/receive a wireless signal in a frequency band that is different from the frequency band of the wireless signal transmitted/received by the first radiating conductors.
    Type: Application
    Filed: May 20, 2019
    Publication date: September 5, 2019
    Inventors: Young-Ju LEE, Seung-Tae KO, Hyun-Jin KIM
  • Patent number: 10351885
    Abstract: The present invention relates to a mutant microorganism having the ability to produce 5-aminolevulinic acid, and more particularly, to a mutant microorganism having the ability to produce 5-aminolevulinic acid wherein a glutamyl-tRNA reductase-encoding gene is introduced in a glutamic acid-producing microorganism, and to a method for producing 5-aminolevulinic acid using the same. According to the present invention, 5-aminolevulinic acid that is useful in the medical or agricultural field can be produced in a significantly higher yield than that of conventional production methods.
    Type: Grant
    Filed: July 24, 2016
    Date of Patent: July 16, 2019
    Assignee: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Sung Ok Han, Seung-Kyou You, Jeong-Eun Hyeon, Young-jin Ko
  • Publication number: 20190198429
    Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is disposed on the stopper layer; first metal bumps disposed on the connection pads; an encapsulant covering at least portions of each of the frame, the semiconductor chip, and the first metal bumps and filling at least portions of the recess portion; a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers and the connection pads to each other; and a first blocking structure disposed on walls of the recess portion to surround side surfaces of the semiconductor chip.
    Type: Application
    Filed: June 19, 2018
    Publication date: June 27, 2019
    Inventors: Myung Sam KANG, Young Gwan KO, Jeong Ho LEE, Shang Hoon SEO, Yong Jin SEOL
  • Publication number: 20190164926
    Abstract: A fan-out semiconductor package includes a core member having a through-hole in which a semiconductor chip is disposed. The semiconductor chip has an active surface having connection pads disposed thereon and an inactive surface opposing the active surface. An encapsulant encapsulates at least a portion of the semiconductor chip. A connection member is disposed on the active surface of the semiconductor chip and includes a redistribution layer electrically connected to the connection pads of the semiconductor chip. A passivation layer is disposed on the connection member. The fan-out semiconductor package further has a slot spaced part from the through-hole and penetrating through at least a portion of the core member or the passivation layer.
    Type: Application
    Filed: June 18, 2018
    Publication date: May 30, 2019
    Inventors: Yong Jin Seol, Myung Sam Kang, Young Gwan Ko