Abstract: A plasma processing apparatus including an electrostatic chuck supporting a wafer; a focus ring disposed to surround an outer circumferential surface of the wafer; an insulation ring disposed to surround an outer circumferential surface of the focus ring; and an edge ring supporting lower portions of the focus ring and the insulation ring, the edge ring being spaced apart from the electrostatic chuck and surrounding an outer circumferential surface of the electrostatic chuck; wherein the edge ring includes a flow channel containing a fluid therein.

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

Abstract: Provided is a touch panel. The touch panel includes a substrate and an electrode member disposed on the substrate. The electrode member includes a base material for electrode having first and second surfaces opposite to each other, a first electrode disposed on the first surface, and a second electrode disposed on the second surface.

Abstract: Provided is a method for manufacturing a touch panel. In the method, a substrate is prepared, a transparent electrode is formed on the substrate, an interconnection electrode material is applied to the substrate by printing, an interconnection electrode is formed by drying the interconnection electrode material, and a circuit board is disposed on the interconnection electrode.

Abstract: A semiconductor device includes: a substrate including a channel region; a gate dielectric a tunneling layer, a charge storage layer, and a blocking layer sequentially disposed on the channel region; and a gate electrode disposed on the gate dielectric, wherein the tunneling layer has variations in nitrogen concentrations in a direction perpendicular to the channel region, and has a maximum nitrogen concentration in a position shifted from a center of the tunneling layer toward the charge storage layer.

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

Abstract: Tunnel insulation layer structures and methods of manufacturing the same are disclosed. The tunnel insulation layer structures may include a first tunnel insulation layer, a second tunnel insulation layer, a third tunnel insulation layer, a fourth tunnel insulation layer and a fifth tunnel insulation layer. The first tunnel insulation layer on a substrate has a first band gap energy. The second tunnel insulation layer on the first tunnel insulation layer has a second band gap energy which is lower than the first band gap energy. The third tunnel insulation layer on the second tunnel insulation layer has a third band gap energy which is higher than the second band gap energy. The fourth tunnel insulation layer on the third tunnel insulation layer has a fourth band gap energy which is lower than the third band gap energy. The fifth tunnel insulation layer on the fourth tunnel insulation layer has a fifth band gap energy which is higher than the fourth band gap energy.

Abstract: A method for fabricating a substrate includes forming a first substrate including a thin film transistor array, and inspecting a first surface of an inspecting device, wherein inspecting the first surface of the inspection device includes: generating first measurement data by detecting a first measurement light that is parallel to a surface of an inspection region in the first surface, generating second measurement data by detecting a second measurement light that is parallel to the surface of the inspection region, and inspecting a state of a surface of the inspection region by comparing the first measurement data with the second measurement data.

Abstract: Provided are a dummy wafer, a thin-film forming method, and a method of fabricating a semiconductor device using the same. The dummy wafer includes an insulating substrate with a first surface opposite a second surface, and a plurality of openings formed in the insulating substrate. The plurality of openings penetrate at least a portion of the insulating substrate in a direction from the first surface toward the second surface. The first and second surfaces of the insulating substrate, and an inner surface of each of the plurality of openings, include protrusions.

Abstract: A thin film deposition apparatus, including a processing chamber; a boat in the processing chamber, the boat to accommodate a plurality of substrates therein; and a nozzle to supply a source gas to the processing chamber to form a thin film on each of the substrates, the nozzle including a plurality of T-shaped nozzle pipes, each of the T-shaped nozzle pipes including a first pipe having closed ends and a second pipe coupled to a middle portion of the first pipe.

Abstract: A wafer processing apparatus may include a reaction tube extending in a vertical direction and defining a process chamber for receiving a boat that holds a plurality of wafers. A gas injector may be configured to supply a reaction gas into the process chamber and may include a gas distributor extending in the vertical direction in the reaction tube. The gas injector may have a plurality of ejection holes for spraying the reaction gas. An inner diameter of the gas distributor may be at least 10 mm, and a sectional area ratio of the total sectional area of the ejection holes to a sectional area of the gas distributor is about 0.3 or less.

Abstract: A touch panel according to the embodiment includes a substrate; a first electrode formed on the substrate in a first direction and including a plurality of sensor parts and connection parts connecting the sensor parts with each other; and a second electrode formed in a second direction crossing the first direction while being insulated from the first electrode and including a plurality of sensor parts and connection parts connecting the sensor parts with each other. The sensor parts and the connection parts include transparent conductive materials, and the connection parts have resistance lower than resistance of the sensor parts in at least one of the first and second electrodes.

Abstract: Provided are a three dimensional semiconductor memory device and a method of fabricating the same. In the three dimensional semiconductor memory device, a stack of gate electrodes and insulating layers may be formed on a substrate, a channel structure may extend through the stack and connect to the substrate. A blocking insulating layer, a charge storing layer and a tunnel insulating layer may be formed between each gate electrode and the channel structure. The tunnel insulating layer may include a high-k dielectric layer with a low charge trap site density. The tunnel insulating layer may also include a first and a second tunnel insulating layers, and the high-k dielectric layer is provided between the first and second tunnel insulating layers.

Abstract: A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer.

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

Abstract: A gas injector may comprise: a gas introduction tube configured to introduce reaction gas into a reaction tube from a gas supply source; and/or a gas distributor connected to the gas introduction tube, extending from the gas introduction tube in a direction within the reaction tube, including a plurality of ejection holes in an inner surface of the gas distributor, and having an arc shape extending in a circumferential direction of the reaction tube. The ejection holes may be spaced apart from each other in the extending direction of the gas distributor, and are configured to spray the reaction gas.

Abstract: Provided are a three dimensional semiconductor memory device and a method of fabricating the same. In the three dimensional semiconductor memory device, a stack of gate electrodes and insulating layers may be formed on a substrate, a channel structure may extend through the stack and connect to the substrate. A blocking insulating layer, a charge storing layer and a tunnel insulating layer may be formed between each gate electrode and the channel structure. The tunnel insulating layer may include a high-k dielectric layer with a low charge trap site density. The tunnel insulating layer may also include a first and a second tunnel insulating layers, and the high-k dielectric layer is provided between the first and second tunnel insulating layers.

Abstract: A substrate processing apparatus including a process chamber configured to receive a plurality of substrates oriented in a horizontal manner and vertically arranged with respect to the process chamber, a process gas supply unit configured to supply at least one process gas to the process chamber through a process gas supply nozzle, the process gas supply nozzle along an inner wall of the process chamber in a direction in which the substrates are sacked, an exhaust unit configured to exhaust the process gas from the process chamber, and a blocking gas supply unit configured to supply a blocking gas through a blocking gas injector provided in a circumferential direction of the process chamber such that a flow of the process gas in the process chamber is controlled may be provided.

Abstract: A semiconductor device includes: a substrate including a channel region; a gate dielectric a tunneling layer, a charge storage layer, and a blocking layer sequentially disposed on the channel region; and a gate electrode disposed on the gate dielectric, wherein the tunneling layer has variations in nitrogen concentrations in a direction perpendicular to the channel region, and has a maximum nitrogen concentration in a position shifted from a center of the tunneling layer toward the charge storage layer.