Patents by Inventor Young-Jin Wee
Young-Jin Wee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7638423Abstract: A method of forming wires of a semiconductor device including forming a first metal wire on a semiconductor substrate; forming a first insulating film on the first metal wire; etching a portion of the first insulating film to expose a surface portion of the first metal wire; forming a first barrier metal film on sidewalls of the opening and the exposed first metal wire; etching a portion of the first barrier metal film on the first metal wire to expose a surface portion of the first metal wire; performing a heat treatment process on the exposed surface portion of the first metal wire to improve surface roughness; and forming a second wire by filling the opening using a conductive material.Type: GrantFiled: February 2, 2007Date of Patent: December 29, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-eun Lee, Young-jin Wee, Andrew-tae Kim, Young-joon Moon
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Patent number: 7635645Abstract: Methods for forming an interconnection line and interconnection line structures are disclosed. The method includes forming an interlayer insulating layer on a semiconductor substrate, wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer is formed on the interlayer insulating layer. An oxide capping layer is formed on the oxidation barrier layer. A via hole is in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern is formed within the via hole.Type: GrantFiled: January 4, 2005Date of Patent: December 22, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-Woo Lee, Hong-Jae Shin, Jae-Hak Kim, Young-Jin Wee, Seung-Jin Lee, Ki-Kwan Park
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Patent number: 7341908Abstract: Provided are a semiconductor device including a reliable interconnect and a method of manufacturing the same. The semiconductor device includes a substrate, an inter-metal dielectric (IMD) pattern having an opening, an amorphous metallic nitride layer formed on the inner surface of the opening, a diffusion barrier layer formed on the amorphous metallic nitride layer, and a conductive layer filled into the opening having the diffusion barrier layer.Type: GrantFiled: January 30, 2006Date of Patent: March 11, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Bong-seok Suh, Seung-man Choi, Hong-jae Shin, Young-jin Wee
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Publication number: 20070224855Abstract: A method of forming wires of a semiconductor device including forming a first metal wire on a semiconductor substrate; forming a first insulating film on the first metal wire; etching a portion of the first insulating film to expose a surface portion of the first metal wire; forming a first barrier metal film on sidewalls of the opening and the exposed first metal wire; etching a portion of the first barrier metal film on the first metal wire to expose a surface portion of the first metal wire; performing a heat treatment process on the exposed surface portion of the first metal wire to improve surface roughness; and forming a second wire by filling the opening using a conductive material.Type: ApplicationFiled: February 2, 2007Publication date: September 27, 2007Inventors: Jung-eun Lee, Young-jin Wee, Andrew-tae Kim, Young-joon Moon
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Patent number: 7192864Abstract: The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is formed to fill the via hole. A photoresist pattern is formed on the via filling material. The via filling material and the interlayer insulating layer are anisotropically etched using the photoresist pattern as an etch mask to form a trench. A residual portion of the via filling material is removed using two wet etch processes. After removing the residual portion of the via filling material, a conductive layer pattern is formed in the via hole and the trench.Type: GrantFiled: February 4, 2005Date of Patent: March 20, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-Woo Lee, Hong-Jae Shin, Jae-Hak Kim, Young-Jin Wee, Seung-Jin Lee, Ki-Kwan Park
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Publication number: 20060170103Abstract: Provided are a semiconductor device including a reliable interconnect and a method of manufacturing the same. The semiconductor device includes a substrate, an inter-metal dielectric (IMD) pattern having an opening, an amorphous metallic nitride layer formed on the inner surface of the opening, a diffusion barrier layer formed on the amorphous metallic nitride layer, and a conductive layer filled into the opening having the diffusion barrier layer.Type: ApplicationFiled: January 30, 2006Publication date: August 3, 2006Inventors: Bong-seok Suh, Seung-man Choi, Hong-Jae Shin, Young-jin Wee
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Publication number: 20050176236Abstract: The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is formed to fill the via hole. A photoresist pattern is formed on the via filling material. The via filling material and the interlayer insulating layer are anisotropically etched using the photoresist pattern as an etch mask to form a trench. A residual portion of the via filling material is removed using two wet etch processes. After removing the residual portion of the via filling material, a conductive layer pattern is formed in the via hole and the trench.Type: ApplicationFiled: February 4, 2005Publication date: August 11, 2005Inventors: Kyoung-Woo Lee, Hong-Jae Shin, Jae-Hak Kim, Young-Jin Wee, Seung-Jin Lee, Ki-Kwan Park
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Publication number: 20050161821Abstract: Methods for forming an interconnection line and interconnection line structures are disclosed. The method includes forming an interlayer insulating layer on a semiconductor substrate, wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer is formed on the interlayer insulating layer. An oxide capping layer is formed on the oxidation barrier layer. A via hole is in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern is formed within the via hole.Type: ApplicationFiled: January 4, 2005Publication date: July 28, 2005Inventors: Kyoung-Woo Lee, Hong-Jae Shin, Jae-Hak Kim, Young-Jin Wee, Seung-Jin Lee, Ki-Kwan Park
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Patent number: 6842028Abstract: In the present invention, an apparatus of testing a leakage protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern, a serpentine-like pattern and means of applying a bias to the patterns and forms a maximum field region at an interconnection formed around a via, i.e., at the end of a tooth portion composing the comb-like pattern. In one structure of the present invention, the comb-like pattern is formed at one level, and the serpentine-like pattern has a plurality of unit parts corresponding to the tooth portions, respectively, and connection parts connecting the neighboring two unit parts. Each of the unit parts is formed at the same level with the comb-like pattern and spaced apart from the tooth portion by a minimum design length according to a design rule.Type: GrantFiled: January 27, 2004Date of Patent: January 11, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Sang Song, Jung-Woo Kim, Chang-Sub Lee, Sam-Young Kim, Young-Jin Wee, Ki-Chul Park
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Publication number: 20040189338Abstract: In the present invention, an apparatus of testing a leakage protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern, a serpentine-like pattern and means of applying a bias to the patterns and forms a maximum field region at an interconnection formed around a via, i.e., at the end of a tooth portion composing the comb-like pattern. In one structure of the present invention, the comb-like pattern is formed at one level, and the serpentine-like pattern has a plurality of unit parts corresponding to the tooth portions, respectively, and connection parts connecting the neighboring two unit parts. Each of the unit parts is formed at the same level with the comb-like pattern and spaced apart from the tooth portion by a minimum design length according to a design rule.Type: ApplicationFiled: January 27, 2004Publication date: September 30, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Won-Sang Song, Jung-Woo Kim, Chang-Sub Lee, Sam-Young Kim, Young-Jin Wee, Ki-Chul Park
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Patent number: 6693446Abstract: In the present invention, an apparatus of testing leakage current protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern composed of a length portion, multiple tooth portions which are connected orthogonally to the length portion, and vias which are formed vertically from the ends of the tooth portions, respectively, through an interlayer dielectric layer. Additionally the apparatus has a serpentine-like pattern including a length parallel part or a connection part which is running parallel to the length portion, a tooth parallel part which is parallel to the tooth portion and formed at a level different from the level of the connection part or the length parallel part, and vias connecting them. The via of the comb-like pattern is located at the central position between the neighboring two vias of the serpentine-like pattern.Type: GrantFiled: April 1, 2002Date of Patent: February 17, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Sang Song, Jung-Woo Kim, Chang-Sub Lee, Sam-Young Kim, Young-Jin Wee, Ki-Chul Park
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Patent number: 6690187Abstract: In the present invention, an apparatus of testing a leakage protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern, a serpentine-like pattern and means of applying a bias to the patterns and forms a maximum field region at an interconnection formed around a via, i.e., at the end of a tooth portion composing the comb-like pattern. In one structure of the present invention, the comb-like pattern is formed at one level, and the serpentine-like pattern has a plurality of unit parts corresponding to the tooth portions, respectively, and connection parts connecting the neighboring two unit parts. Each of the unit parts is formed at the same level with the comb-like pattern and spaced apart from the tooth portion by a minimum design length according to a design rule.Type: GrantFiled: April 1, 2002Date of Patent: February 10, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Sang Song, Jung-Woo Kim, Chang-Sub Lee, Sam-Young Kim, Young-Jin Wee, Ki-Chul Park
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Publication number: 20030020497Abstract: In the present invention, an apparatus of testing leakage current protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern composed of a length portion, multiple tooth portions which are connected orthogonally to the length portion, and vias which are formed vertically from the ends of the tooth portions, respectively, through an interlayer dielectric layer. Additionally the apparatus has a serpentine-like pattern including a length parallel part or a connection part which is running parallel to the length portion, a tooth parallel part which is parallel to the tooth portion and formed at a level different from the level of the connection part or the length parallel part, and vias connecting them. The via of the comb-like pattern is located at the central position between the neighboring two vias of the serpentine-like pattern.Type: ApplicationFiled: April 1, 2002Publication date: January 30, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: Won-Sang Song, Jung-Woo Kim, Chang-Sub Lee, Sam-Young Kim, Young-Jin Wee, Ki-Chul Park
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Publication number: 20030020507Abstract: In the present invention, an apparatus of testing a leakage protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern, a serpentine-like pattern and means of applying a bias to the patterns and forms a maximum field region at an interconnection formed around a via, i.e., at the end of a tooth portion composing the comb-like pattern. In one structure of the present invention, the comb-like pattern is formed at one level, and the serpentine-like pattern has a plurality of unit parts corresponding to the tooth portions, respectively, and connection parts connecting the neighboring two unit parts. Each of the unit parts is formed at the same level with the comb-like pattern and spaced apart from the tooth portion by a minimum design length according to a design rule.Type: ApplicationFiled: April 1, 2002Publication date: January 30, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: Won-Sang Song, Jung-Woo Kim, Chang-Sub Lee, Sam-Young Kim, Young-Jin Wee, Ki-Chul Park
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Patent number: 6483162Abstract: A semiconductor device having improved metal line structure has a first dielectric layer formed on a semiconductor substrate, a metal film pattern formed on the first dielectric layer, an interface protection layer on the metal film pattern, and a second dielectric layer on the interface protection layer, wherein the second dielectric layer contains a reactive material, e.g., fluorine, which is prevented by the interface protection layer from diffusing to the metal film pattern and reacting with the metal in the metal film pattern to form a damage film, e.g., metal fluoride, which is a highly resistive material that, if formed on the semiconductor device, would reduce the reliability of the metal film pattern and thus reduce the reliability of the semiconductor device as a whole.Type: GrantFiled: February 20, 2001Date of Patent: November 19, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-chul Kwon, Young-jin Wee, Hong-jae Shin, Sung-jin Kim
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Patent number: 6333260Abstract: A semiconductor device having improved metal line structure has a first dielectric layer formed on a semiconductor substrate, a metal film pattern formed on the first dielectric layer, an interface protection layer on the metal film pattern, and a second dielectric layer on the interface protection layer, wherein the second dielectric layer contains a reactive material, e.g., fluorine, which is prevented by the interface protection layer from diffusing to the metal film pattern and reacting with the metal in the metal film pattern to form a damage film, e.g., metal fluoride, which is a highly resistive material that, if formed on the semiconductor device, would reduce the reliability of the metal film pattern and thus reduce the reliability of the semiconductor device as a whole.Type: GrantFiled: June 24, 1999Date of Patent: December 25, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-chul Kwon, Young-jin Wee, Hong-jae Shin, Sung-jin Kim
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Publication number: 20010006255Abstract: A semiconductor device having improved metal line structure has a first dielectric layer formed on a semiconductor substrate, a metal film pattern formed on the first dielectric layer, an interface protection layer on the metal film pattern, and a second dielectric layer on the interface protection layer, wherein the second dielectric layer contains a reactive material, e.g., fluorine, which is prevented by the interface protection layer from diffusing to the metal film pattern and reacting with the metal in the metal film pattern to form a damage film, e.g., metal fluoride, which is a highly resistive material that, if formed on the semiconductor device, would reduce the reliability of the metal film pattern and thus reduce the reliability of the semiconductor device as a whole.Type: ApplicationFiled: February 20, 2001Publication date: July 5, 2001Inventors: Dong-chul Kwon, Young-jin Wee, Hong-jae Shin, Sung-jin Kim
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Patent number: 6249056Abstract: The present invention provides a structure and a method for formation of interconnect having a barrier layer, aluminum layer on the barrier layer, a reaction prevention layer on the aluminum layer, an antireflective coating layer on the reaction prevention layer, a dielectric layer, a via, a conductive plug, and another aluminum layer on the via and the dielectric layer. This structure prevents interconnects from contact resistance failure caused by an aluminum nitride film AlF, a titanium fluorine film TixFF, aluminum overetching, and aluminum consumption. As a result of this invention, via electromigration and aluminum line electromigration characteristics are improved in semiconductor devices.Type: GrantFiled: November 1, 1999Date of Patent: June 19, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-chul Kwon, Young-Jin Wee
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Patent number: 6004876Abstract: The present invention provides a structure and a method for formation of interconnect having a barrier layer, aluminum layer on the barrier layer, a reaction prevention layer on the aluminum layer, an antireflective coating layer on the reaction prevention layer, a dielectric layer, a via, a conductive plug, and another aluminum layer on the via and the dielectric layer. This structure prevents interconnects from contact resistance failure caused by an aluminum nitride film AlF, a titanium fluorine film Ti.sub.x F, aluminum overetching, and aluminum consumption. As a result of this invention, via electro-migration and aluminum line electromigration characteristics are improved in semiconductor devices.Type: GrantFiled: August 14, 1998Date of Patent: December 21, 1999Assignee: Samsung Electronics, Co., Ltd.Inventors: Dong-chul Kwon, Young-Jin Wee
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Patent number: 5814556Abstract: A method for forming a metal layer of an ultra-thin film according to metal deposition conditions and a method for forming metal wiring by filling a high aspect-ratio contact hole using cooling step prior to depositing the metal layer. In particular, the additional cooling process is performed before the process of depositing the metal layer and then the deposition process is performed in a state where the temperature of the wafer has been cooled down to a temperature in the range between -25.degree. C. and room temperature. The surface morphology of the deposited metal layer is improved and a continuous ultra-thin film can be obtained. Also, the aluminum filling characteristics in the contact hole having a high aspect-ratio are improved.Type: GrantFiled: August 15, 1996Date of Patent: September 29, 1998Assignee: Samsung Electronics Co., Ltd.Inventors: Young-jin Wee, In-seon Park, Sang-in Lee