Abstract: The invention relates to a display apparatus that receives a broadcast signal and includes a selection input, an on screen display (OSD) generator and a display part to display a video signal thereon, including a memory to store information about broadcast standards corresponding to regional information of the display apparatus; and a controller to control the OSD generator under predetermined conditions to display an OSD menu on the display part to select the regional information, and set the broadcast standards of the display apparatus based on the information about the broadcast standards stored in the memory when a user selects the regional information through the selection input.

Abstract: Provided is a data input unit of a synchronous semiconductor memory device comprising: means for generating a rising edge signal and a falling edge signal at a rising edge and a falling edge of a data strobe signal DQS to be input; means for generating a second falling edge signal whenever two falling edge signals are generated in response to the data strobe signal; a data transforming means for dividing input data into four and latching the four divided data in response to the rising edge signal and falling edge signal, and then latching again the four divided data in response to the second falling edge signal; and a global input/output signal generator for transmitting the data from the data transforming means to a global input/output line in response to a strobe clock.

Abstract: A synchronous memory device which generates a data output enable signal corresponding to a set CAS latency mode including: a control clock generator for generating an A-type first control clock and a B-type first control clock; a first redundancy enable signal generator for shifting an internal read signal by a predetermined interval in synchronization with one of the A-type first control clock and the B-type first control clock and generating a plurality of first redundancy enable signals; a second redundancy enable signal generator for synchronizing the plurality of first redundancy enable signals with a DLL clock and generating a plurality of second redundancy enable signals; and an output enable signal generator for selecting one redundancy enable signal corresponding to the set CAS latency mode among the first redundancy enable signals and the second redundancy enable signals and generating the selected redundancy enable signal as the data output enable signal.

Abstract: Disclosed is a photocatalytic coating sol composition and the method for preparing the same. The photocatalityc coating sol composition comprising 0.1% to 20% by weight of a photo-catalyst, 0.1% to 10% by weight of an inorganic adsorbent, 1% to 20% by weight of an inorganic binder, 55% to 95% by weight of an organic solvent and if necessary 0.1% by weight to 10% by weight of a metal compound. Specifically, the present invention can remove harmful substances by coating photocatalytic coating sol composition prepared from photocatalyst, inorganic adsorbent, inorganic binder, metal compound and organic solvent on metal filter such as aluminum etc., and plastic filter such as polyethylene and polypropylene etc. used in environmental contaminants treatment system or air conditioning plant such as air-conditioner and air-cleaner, according to any one of and ordinary coating techniques such as spray method or dipping method etc. at room temperature.

Abstract: A synchronous memory device which generates a data output enable signal corresponding to a set CAS latency mode including: a control clock generator for generating an A-type first control clock and a B-type first control clock; a first redundancy enable signal generator for shifting an internal read signal by a predetermined interval in synchronization with one of the A-type first control clock and the B-type first control clock and generating a plurality of first redundancy enable signals; a second redundancy enable signal generator for synchronizing the plurality of first redundancy enable signals with a DLL clock and generating a plurality of second redundancy enable signals; and an output enable signal generator for selecting one redundancy enable signal corresponding to the set CAS latency mode among the first redundancy enable signals and the second redundancy enable signals and generating the selected redundancy enable signal as the data output enable signal.

Abstract: A semiconductor device for performing an N-bit prefetch operation, N being a positive integer includes a data strobe buffering means for generating N number of align control signals based on a data strobe signal and a external clock signal; a receiving block in response to N−1 number of the align control signals for receiving N-bit data and outputting the N-bit data in a parallel fashion; and a outputting block in response to the remaining align control signal for receiving the N-bit data in the parallel fashion and synchronizing the N-bit data with the remaining align control signal having a N/2 external clock period to thereby generating the synchronized N-bit data as a prefetched data.

Abstract: A semiconductor memory device minimizes a data accessing time. For the purpose, it includes a first control signal generator for producing a first control signal by logically combining a pipelatch-in signal and a start-odd start-even data output control signal, a second control signal generator for producing an odd control signal by logically combining an odd data enable signal for outputting odd-numbered data and a control signal for accessing the odd-numbered data in response to a start address, and generating an even control signal by logically combining an even data enable signal for outputting even-numbered data and a control signal for accessing the even-numbered data in response to the start address, a first accessing unit for accessing input data in response to the first control signal, a latch for temporarily storing data outputted from the first data accessing unit, and a second accessing unit for secondly accessing the data stored at the latch, thereby outputting secondly accessed data.

Abstract: A film coating apparatus has a nozzle body and a coating material spreading element having an injection hole communicated with the inside of the nozzle body, and formed integrally with the nozzle body. The apparatus further has a rotation support element and a fixing element for rotatably supporting both ends of a piston for a fixed displacement swash plate type compressor and a pair of first coating material applying elements moveably installed above the rotation support element. The first coating material applying elements have a pair of first nozzles which apply coating material in uniform thickness to circumferential outer surfaces of both head parts of the piston. A second coating material applying element is installed above the fixing element such that it can be moved upward and downward and slid laterally to apply coating material in uniform thickness to a bridge part of the piston.

Abstract: Provided is a data input unit of a synchronous semiconductor memory device comprising: means for generating a rising edge signal and a falling edge signal at a rising edge and a falling edge of a data strobe signal DQS to be input; means for generating a second falling edge signal whenever two falling edge signals are generated in response to the data strobe signal; a data transforming means for dividing input data into four and latching the four divided data in response to the rising edge signal and falling edge signal, and then latching again the four divided data in response to the second falling edge signal; and a global input/output signal generator for transmitting the data from the data transforming means to a global input/output line in response to a strobe clock.

Abstract: A semiconductor memory device includes an advanced prefetching block for prefetching more bit data at once and effectively arranging the prefetched data so as to reduce an address access time of the semiconductor memory device. The semiconductor memory device having four pipelining latches for prefetching 4-bit data outputted from at least one bank in response to a start address of the 4-bit data and control signals includes a first data multiplexing unit, a second data multiplexing unit, a third order multiplexing unit and a forth order multiplexing unit.

Abstract: A semiconductor memory device includes an advanced prefetching block for prefetching more bit data at once and effectively arranging the prefetched data so as to reduce an address access time of the semiconductor memory device. The semiconductor memory device having four pipelining latches for prefetching 4-bit data outputted from at least one bank in response to a start address of the 4-bit data and control signals includes a first data multiplexing unit, a second data multiplexing unit, a third order multiplexing unit and a forth order multiplexing unit.

Abstract: A semiconductor memory device minimizes a data accessing time. For the purpose, it includes a first control signal generator for producing a first control signal by logically combining a pipelatch-in signal and a start-odd start-even data output control signal, a second control signal generator for producing an odd control signal by logically combining an odd data enable signal for outputting odd-numbered data and a control signal for accessing the odd-numbered data in response to a start address, and generating an even control signal by logically combining an even data enable signal for outputting even-numbered data and a control signal for accessing the even-numbered data in response to the start address, a first accessing unit for accessing input data in response to the first control signal, a latch for temporarily storing data outputted from the first data accessing unit, and a second accessing unit for secondly accessing the data stored at the latch, thereby outputting secondly accessed data.

Abstract: A synchronous memory device which comprises global I/O lines for data input and output from and to a memory core and a pipeline latch circuit for latching data from the global I/O lines. The synchronous memory device includes a circuit that precharges the global I/O lines when a read command signal interrupts a write operation signal, and disables the pipeline latch circuit in order to prevent write data on the global I/O lines from being latched in the pipeline latch circuit. Accordingly, the write data is prevented from being transferred to the pipeline latch circuit at an early stage of the read operation.

Abstract: A global input/output precharge apparatus includes a latch for cross-coupling and latching a global input/output line and a complementary global input/output line; a global input/output line delay for delaying the global input/output line and the complementary global input/output line by a predetermined time delay; a global input/output line precharge logic for pre-charging the global input/output line feed-backed from the global input/output line delay; a first precharge logic for applying a power voltage to the global input/output line when a first logic state is feed-backed on the output of the global input/output line precharge logic and applying a ground voltage to the global input/output line when a second logic state is feed-backed on the output of the global input/output line precharge logic; and a second precharge logic for applying the power voltage to the complementary global input/output line when the first logic state is feed-backed on the output of the global input/output line precharge logic an

Abstract: Disclosed inventions include circuits and methods for controlling a plurality of data input buffers and a plurality data strobe buffers in a semiconductor memory device. High speed operation can be achieved by operating the plurality of data input buffers and the plurality of data strobe buffers in response to a buffer control signal generated faster than an input data, synchronized with internal rising and falling clock signals. A first internal falling clock signal generator generates a first internal falling clock signal in response to an external clock signal. A first internal rising clock signal generator generates a first internal rising clock signal in response to the external clock signal. A buffer controller generates a buffer control signal in response to the first and falling and rising clock signals. The plurality of data input buffers and the plurality of data strobe buffer are enabled or disabled in response to the buffer control signal.

Abstract: A synchronous memory device which comprises global I/O lines for data input and output from and to a memory core and a pipeline latch circuit for latching data from the global I/O lines. The synchronous memory device includes a circuit that precharges the global I/O lines when a read command signal interrupts a write operation signal, and disables the pipeline latch circuit in order to prevent write data on the global I/O lines from being latched in the pipeline latch circuit. Accordingly, the write data is prevented from being transferred to the pipeline latch circuit at an early stage of the read operation.

Abstract: Disclosed are a film coating nozzle, and an apparatus and a method for coating a compressor piston using the same. The film coating nozzle comprises a nozzle body configured to supply coating material; and coating material spreading means defined with a coating material injection hole which is communicated with the inside of the nozzle body, and formed integrally with the nozzle body to spread to a uniform film thickness coating material applied to a surface of a product, in such a way as to remove excess coating material.

Abstract: Disclosed inventions include circuits and methods for controlling a plurality of data input buffers and a plurality data strobe buffers in a semiconductor memory device. High speed operation can be achieved by operating the plurality of data input buffers and the plurality of data strobe buffers in response to a buffer control signal generated faster than an input data, synchronized with internal rising and falling clock signals. A first internal falling clock signal generator generates a first internal falling clock signal in response to an external clock signal. A first internal rising clock signal generator generates a first internal rising clock signal in response to the external clock signal. A buffer controller generates a buffer control signal in response to the first and falling and rising clock signals. The plurality of data input buffers and the plurality of data strobe buffer are enabled or disabled in response to the buffer control signal.

Abstract: A global input/output precharge apparatus includes a latch for cross-coupling and latching a global input/output line and a complementary global input/output line; a global input/output line delay for delaying the global input/output line and the complementary global input/output line by a predetermined time delay; a global input/output line precharge logic for pre-charging the global input/output line feed-backed from the global input/output line delay; a first precharge logic for applying a power voltage to the global input/output line when a first logic state is feed-backed on the output of the global input/output line precharge logic and applying a ground voltage to the global input/output line when a second logic state is feed-backed on the output of the global input/output line precharge logic; and a second precharge logic for applying the power voltage to the complementary global input/output line when the first logic state is feed-backed on the output of the global input/output line precharge logic an