Abstract: A display substrate including a lower common electrode disposed on a substrate, an insulating layer disposed on the lower common electrode, a gate pattern including a gate electrode disposed on the insulating layer and a common electrode contact part and a direct contact part spaced apart from the gate electrode, a gate insulating layer disposed on the gate pattern, a semiconductor layer disposed on the gate insulating layer, an etch stopping layer disposed on the gate insulating layer, source and drain electrodes disposed on the etch stopping layer, pixel part extending from the source and drain electrodes, a first conductive layer connected to the common electrode contact part, a second conductive layer connected to the direct contact part, and a passivation layer disposed on the source and drain electrodes, the first conductive layer, and the second conductive layer.

Abstract: Disclosed are a display substrate, of which productivity is improved by decreasing five mask (M) processes utilized for fabricating the display substrate used in a liquid crystal display device in a horizontal field (Plane to Line Switching (PLS)) mode to four mask processes, and a method of fabricating the same.

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract: A method of manufacturing a color filter substrate includes forming a plurality of trenches having a predetermined depth by etching a surface of a transparent substrate, disposing a color filter material in the plurality of trenches to form a color filter layer, and forming a transparent electrode on the transparent substrate including the color filter layer therein.

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract: A liquid crystal display and a method of fabricating a liquid crystal display (LCD), the LCD including a substrate; gate wiring including a gate pad, a gate electrode, and a gate line, which are formed on the substrate; a gate insulating layer disposed on the gate wiring; an electrode pattern including a connecting electrode, which is disposed on the gate insulating layer and is electrically connected to the gate pad, a source electrode and a drain electrode, which partially overlap the gate electrode; a pixel electrode, which is electrically connected to the drain electrode; a data line, which intersects the gate line; a semiconductor layer disposed on the gate electrode; first auxiliary wiring overlapping the data line and spaced from the semiconductor layer; and second auxiliary wiring overlapping the gate line.

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract: A liquid crystal display and a manufacturing method thereof include a planar-shaped common electrode disposed directly on a common voltage line, and a semiconductor layer disposed on the common electrode and a gate line, serving as a gate insulating layer. Accordingly, it is possible to prevent signal delay of the common voltage and lower the manufacturing cost by disposing a common electrode and a pixel electrode on one substrate and disposing a common electrode directly on a common voltage line.

Abstract: A liquid crystal display and a manufacturing method thereof are disclosed, whereby a common electrode having a planar shape is formed directly on a common voltage line, and a semiconductor layer is formed on the common electrode and a gate line. The common electrode and a pixel electrode are formed on one substrate, with the common electrode being formed directly on the common voltage line. Accordingly, the costs of manufacturing the liquid crystal display may be reduced, and signal delay of a common voltage can be prevented.

Abstract: A thin-film transistor (TFT) substrate including a first region including a semiconductor layer, a first etch barrier layer covering the semiconductor layer, a first contact hole and a second contact hole, which are formed through the first etch barrier layer, a source electrode, which is disposed on the first etch barrier layer and is electrically connected to the semiconductor layer via the first contact hole, a drain electrode, which is disposed on the first etch barrier layer to be isolated from the source electrode, is electrically connected to the semiconductor layer via the second contact hole and has a transparent conductive oxide layer and a metal layer, and a pixel electrode, which is disposed on the first etch barrier layer and includes the transparent conductive oxide layer.

Abstract: A thin film transistor substrate includes a gate metal pattern comprising a gate line extending in a first direction and a gate electrode electrically connected to the gate line, an active pattern overlapping the gate electrode, an etch-stop layer disposed on the active pattern and having a first through hole and a second through hole adjacent to the first through hole, a data metal pattern comprising a data line extending in a second direction crossing the first direction, a source electrode electrically connected to the active pattern through the first through hole and a drain electrode electrically connected to the active pattern through the second through hole and a first passivation layer disposed on the data metal pattern.

Abstract: A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon.

Abstract: A display substrate and its fabricating method have been disclosed. In a horizontal-field-mode liquid crystal display device, while maintaining five mask processes, additional direct contact has been formed to implement a narrow bezel.

Abstract: A display substrate including a lower common electrode disposed on a substrate, an insulating layer disposed on the lower common electrode, a gate pattern including a gate electrode disposed on the insulating layer and a common electrode contact part and a direct contact part spaced apart from the gate electrode, a gate insulating layer disposed on the gate pattern, a semiconductor layer disposed on the gate insulating layer, an etch stopping layer disposed on the gate insulating layer, source and drain electrodes disposed on the etch stopping layer, pixel part extending from the source and drain electrodes, a first conductive layer connected to the common electrode contact part, a second conductive layer connected to the direct contact part, and a passivation layer disposed on the source and drain electrodes, the first conductive layer, and the second conductive layer.

Abstract: Disclosed are a display substrate, of which productivity is improved by decreasing five mask (M) processes utilized for fabricating the display substrate used in a liquid crystal display device in a horizontal field (Plane to Line Switching (PLS)) mode to four mask processes, and a method of fabricating the same.

Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, and a data wire layer disposed on the substrate and including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode. In addition, at least one of the data line, the source electrode or the drain electrode of the data wire layer includes a barrier layer and a main wiring layer disposed on the barrier layer. The main wiring layer includes copper or a copper alloy. Also, the barrier layer includes a metal oxide, and the metal oxide includes zinc.

Abstract: A thin film transistor array panel includes: a gate line including a gate electrode; a first gate insulating layer on the gate line; a semiconductor layer on the first gate insulating layer and overlapping the gate electrode; a second gate insulating layer on the semiconductor layer and the first gate insulating layer, and an opening in the second gate insulating layer and through which the semiconductor layer is exposed; drain and source electrodes on the second gate insulating and semiconductor layers and facing each other; a first field generating electrode; and a second field generating electrode connected to the drain electrode. The semiconductor layer includes an oxide semiconductor layer, and first and second auxiliary layers on the oxide semiconductor layer and separated from each other. An edge of the drain and source electrodes is disposed inside an edge of the first and second auxiliary layers, respectively.

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, and a data wire layer disposed on the substrate and including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode. In addition, at least one of the data line, the source electrode or the drain electrode of the data wire layer includes a barrier layer and a main wiring layer disposed on the barrier layer. The main wiring layer includes copper or a copper alloy. Also, the barrier layer includes a metal oxide, and the metal oxide includes zinc.