Patents by Inventor Young Joon Lee

Young Joon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12189898
    Abstract: A touch sensing system may include, for example, pixels for displaying an input image, data lines, touch electrodes, a timing controller for dividing one frame into a display driving period for displaying the input image and a touch driving period for driving the touch electrodes, a stylus pen for receiving a pen uplink signal during the touch driving period and outputting a pen downlink signal, and a touch sensing circuit for causing the pen uplink signal to be radiated to the stylus pen from the data lines during the touch driving period and for sensing voltages of the touch electrodes based on the pen downlink signal. In another example, a touch sensing system may supply the pen uplink signal, which is to be radiated to the stylus pen, using touch electrodes and reference voltage lines during the touch driving period. Methods of driving a touch sensing system are also disclosed.
    Type: Grant
    Filed: October 27, 2023
    Date of Patent: January 7, 2025
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Young Joon Lee, Sang Hyuck Bae
  • Publication number: 20240256086
    Abstract: A touch sensing system may include, for example, pixels for displaying an input image, data lines, touch electrodes, a timing controller for dividing one frame into a display driving period for displaying the input image and a touch driving period for driving the touch electrodes, a stylus pen for receiving a pen uplink signal during the touch driving period and outputting a pen downlink signal, and a touch sensing circuit for causing the pen uplink signal to be radiated to the stylus pen from the data lines during the touch driving period and for sensing voltages of the touch electrodes based on the pen downlink signal. In another example, a touch sensing system may supply the pen uplink signal, which is to be radiated to the stylus pen, using touch electrodes and reference voltage lines during the touch driving period. Methods of driving a touch sensing system are also disclosed.
    Type: Application
    Filed: October 27, 2023
    Publication date: August 1, 2024
    Applicant: LG DISPLAY CO., LTD.
    Inventors: Young Joon LEE, Sang Hyuck BAE
  • Publication number: 20240249058
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.
    Type: Application
    Filed: December 22, 2023
    Publication date: July 25, 2024
    Inventors: Anna Darling Goldie, Azalia Mirhoseini, Ebrahim Songhori, Wenjie Jiang, Shen Wang, Roger David Carpenter, Young-Joon Lee, Mustafa Nazim Yazgan, Chian-min Richard Ho, Quoc V. Le, James Laudon, Jeffrey Adgate Dean, Kavya Srinivasa Setty, Omkar Pathak
  • Publication number: 20240143885
    Abstract: Aspects of the disclosure provide for eliminating or reducing uniquification of blocks in a chip-level graph of a computer chip, to reduce the size of the graph while still encoding block-specific information. For each group of blocks in the graph generated from a multiply-instantiated block (MIB), a block in the group is selected as a base block. The physical position of the base block is encoded in a reduced graph, and the physical positions of the remaining blocks are encoded as a linear transformation of the physical position of the base block across the face of the chip. Each group of blocks instantiated from the same MIB is represented as a single instance. The reduced graph can be fed into a device configured to perform a circuit component placement process, to identify the placement of circuit components for blocks in the chip in accordance with one or more objectives.
    Type: Application
    Filed: October 25, 2022
    Publication date: May 2, 2024
    Inventors: Myung-Chul Kim, Roger David Carpenter, Debjit Sinha, Paul Kingsley Rodman, Xuyang Jin, Young-Joon Lee
  • Publication number: 20240095424
    Abstract: Aspects of the disclosure are directed to automatically determining floor planning in chips, which factors in memory macro alignment. A deep reinforcement learning (RL) agent can be trained to determine optimal placements for the memory macros, where memory macro alignment can be included as a regularization cost to be added to the placement objective as a RL reward. Tradeoffs between the placement objective and alignment of macros can be controlled by a tunable alignment parameter.
    Type: Application
    Filed: August 18, 2022
    Publication date: March 21, 2024
    Inventors: Ebrahim Mohammadgholi Songhori, Shen Wang, Azalia Mirhoseini, Anna Goldie, Roger Carpenter, Wenjie Jiang, Young-Joon Lee, James Laudon
  • Patent number: 11853677
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: December 26, 2023
    Assignee: Google LLC
    Inventors: Anna Darling Goldie, Azalia Mirhoseini, Ebrahim Songhori, Wenjie Jiang, Shen Wang, Roger David Carpenter, Young-Joon Lee, Mustafa Nazim Yazgan, Chian-min Richard Ho, Quoc V. Le, James Laudon, Jeffrey Adgate Dean, Kavya Srinivasa Setty, Omkar Pathak
  • Patent number: 11702537
    Abstract: A tablet form of an epoxy resin composition for encapsulation of semiconductor elements, where the tablet form of the epoxy resin composition: (i) includes 97 wt % or more of tablets having a diameter of 0.1 mm to less than 2.8 mm and a height of 0.1 mm to less than 2.8 mm, as measured using an ASTM standard sieve; (ii) satisfies the following Equation 1, ? ? ? D × ? ? ? H ? ? ? D + ? ? ? H ? 1.0 , where ?D is a standard deviation of tablet diameters and ?H is a standard deviation of tablet heights, as measured with respect to 50 tablets arbitrarily selected from the tablets; and (iii) the tablets have a compression density of 1.2 g/mL to 1.7 g/mL.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 18, 2023
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Sang Jin Kim, Sang Kyun Kim, Tae Shin Eom, Dong Hwan Lee, Young Joon Lee, Yong Han Cho
  • Patent number: 11655363
    Abstract: A tableted epoxy resin composition for encapsulation of semiconductor devices and a semiconductor device encapsulated using the tableted epoxy resin composition, the tableted epoxy resin composition satisfying the following conditions (i) a proportion of tablets of the tableted epoxy resin composition having a diameter of greater than or equal to 0.1 mm and less than 2.8 mm and a height of greater than or equal to 0.1 mm and less than 2.8 mm is about 97 wt % or more, as measured by sieve analysis using ASTM standard sieves; (ii) the tablets have a packed density of greater than about 1.7 g/mL; and (iii) a ratio of packed density to cured density of the tablets is about 0.6 to about 0.87.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: May 23, 2023
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Sang Jin Kim, Sang Kyun Kim, Tae Shin Eom, Dong Hwan Lee, Young Joon Lee, Yong Han Cho
  • Publication number: 20230117786
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 20, 2023
    Inventors: Anna Darling Goldie, Azalia Mirhoseini, Ebrahim Songhori, Wenjie Jiang, Shen Wang, Roger David Carpenter, Young-Joon Lee, Mustafa Nazim Yazgan, Chian-min Richard Ho, Quoc V. Le, James Laudon, Jeffrey Adgate Dean, Kavya Srinivasa Setty, Omkar Pathak
  • Patent number: 11556690
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: January 17, 2023
    Assignee: Google LLC
    Inventors: Anna Darling Goldie, Azalia Mirhoseini, Ebrahim Songhori, Wenjie Jiang, Shen Wang, Roger David Carpenter, Young-Joon Lee, Mustafa Nazim Yazgan, Chian-min Richard Ho, Quoc V. Le, James Laudon, Jeffrey Adgate Dean, Kavya Srinivasa Setty, Omkar Pathak
  • Publication number: 20220108058
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.
    Type: Application
    Filed: December 17, 2021
    Publication date: April 7, 2022
    Inventors: Anna Darling Goldie, Azalia Mirhoseini, Ebrahim Songhori, Wenjie Jiang, Shen Wang, Roger David Carpenter, Young-Joon Lee, Mustafa Nazim Yazgan, Chian-min Richard Ho, Quoc V. Le, James Laudon, Jeffrey Adgate Dean, Kavya Srinivasa Setty, Omkar Pathak
  • Patent number: 11216609
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: January 4, 2022
    Assignee: Google LLC
    Inventors: Anna Darling Goldie, Azalia Mirhoseini, Ebrahim Songhori, Wenjie Jiang, Shen Wang, Roger David Carpenter, Young-Joon Lee, Mustafa Nazim Yazgan, Chian-Min Richard Ho, Quoc V. Le, James Laudon, Jeffrey Adgate Dean, Kavya Srinivasa Setty, Omkar Pathak
  • Publication number: 20210363379
    Abstract: An epoxy resin composition for semiconductor device encapsulation films, a film for encapsulation of semiconductor devices, and a semiconductor device encapsulated using the same, the epoxy resin composition including a liquid epoxy resin; a curing agent; about 2 wt % to about 10 wt % of a binder resin; and about 50 wt % or more of an oxide, a nitride, a carbide, or a hydroxide of gadolinium, boron, samarium, cadmium, or europium, all wt % being based on a total weight of the epoxy resin composition.
    Type: Application
    Filed: May 12, 2021
    Publication date: November 25, 2021
    Inventors: Seung Woo HONG, Jin Min CHEON, Young Joon LEE
  • Publication number: 20210355344
    Abstract: An epoxy resin composition for encapsulation of semiconductor devices and a semiconductor device encapsulated using the same, the epoxy resin composition including an epoxy resin; a curing agent; and an inorganic filler, wherein the inorganic filler includes gadolinium oxide, samarium oxide, boron nitride, or boron carbide.
    Type: Application
    Filed: May 12, 2021
    Publication date: November 18, 2021
    Inventors: Jin Min CHEON, Young Joon LEE, Seung Woo HONG
  • Publication number: 20210334445
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.
    Type: Application
    Filed: April 22, 2021
    Publication date: October 28, 2021
    Inventors: Anna Darling Goldie, Azalia Mirhoseini, Ebrahim Songhori, Wenjie Jiang, Shen Wang, Roger David Carpenter, Young-Joon Lee, Mustafa Nazim Yazgan, Chian-min Richard Ho, Quoc V. Le, James Laudon, Jeffrey Adgate Dean, Kavya Srinivasa Setty, Omkar Pathak
  • Publication number: 20210313020
    Abstract: Disclosed are a method and an apparatus for rehabilitation training of a cognitive function. A method for rehabilitation training of a cognitive function may comprise the steps of: performing a cognitive function test by a cognitive rehabilitation service server; receiving a cognitive function test result of the cognitive function test by the cognitive rehabilitation service server; determining a rehabilitation method matching the cognitive function test result, by the cognitive rehabilitation service server; and providing a user device with a rehabilitation content according to the rehabilitation method so as to perform rehabilitation training, by the cognitive rehabilitation service server.
    Type: Application
    Filed: June 18, 2021
    Publication date: October 7, 2021
    Inventors: Young Joon LEE, Young Jin YOO, Eun Young KIM, Tae Kwon KIM, Seung Hoon NAM
  • Publication number: 20210005305
    Abstract: Disclosed are a method and an apparatus for rehabilitation training of a cognitive function. A method for rehabilitation training of a cognitive function may comprise the steps of: performing a cognitive function test by a cognitive rehabilitation service server; receiving a cognitive function test result of the cognitive function test by the cognitive rehabilitation service server; determining a rehabilitation method matching the cognitive function test result, by the cognitive rehabilitation service server; and providing a user device with a rehabilitation content according to the rehabilitation method so as to perform rehabilitation training, by the cognitive rehabilitation service server.
    Type: Application
    Filed: November 29, 2018
    Publication date: January 7, 2021
    Inventors: Young Joon LEE, Young Jin YOO, Eun Young KIM, Tae Kwon KIM, Seung Hoon NAM
  • Publication number: 20200199351
    Abstract: A tableted epoxy resin composition for encapsulation of semiconductor devices and a semiconductor device encapsulated using the tableted epoxy resin composition, the tableted epoxy resin composition satisfying the following conditions (i) a proportion of tablets of the tableted epoxy resin composition having a diameter of greater than or equal to 0.1 mm and less than 2.8 mm and a height of greater than or equal to 0.1 mm and less than 2.8 mm is about 97 wt % or more, as measured by sieve analysis using ASTM standard sieves; (ii) the tablets have a packed density of greater than about 1.7 g/mL; and (iii) a ratio of packed density to cured density of the tablets is about 0.6 to about 0.87.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 25, 2020
    Inventors: Sang Jin KIM, Sang Kyun KIM, Tae Shin EOM, Dong Hwan LEE, Young Joon LEE, Yong Han CHO
  • Publication number: 20200140677
    Abstract: A tablet form of an epoxy resin composition for encapsulation of semiconductor elements, where the tablet form of the epoxy resin composition: (i) includes 97 wt % or more of tablets having a diameter of 0.1 mm to less than 2.8 mm and a height of 0.1 mm to less than 2.8 mm, as measured using an ASTM standard sieve; (ii) satisfies the following Equation 1, ? ? ? D × ? ? ? H ? ? ? D + ? ? ? H ? 1.0 , where ?D is a standard deviation of tablet diameters and ?H is a standard deviation of tablet heights, as measured with respect to 50 tablets arbitrarily selected from the tablets; and (iii) the tablets have a compression density of 1.2 g/mL to 1.7 g/mL.
    Type: Application
    Filed: December 20, 2019
    Publication date: May 7, 2020
    Inventors: Sang Jin KIM, Sang Kyun KIM, Tae Shin EOM, Dong Hwan LEE, Young Joon LEE, Yong Han CHO
  • Patent number: 10359830
    Abstract: Disclosed are an optical touch input device which divisionally adjusts optical output of a light emitting unit before and during a touch operation to reduce power consumption, and a driving method thereof, the optical touch input device includes a display panel, a plurality of infrared light emitting elements disposed on two adjacent sides of the display panel, a lens unit disposed on the remaining two adjacent sides of the display panel and reflecting light emitted from the infrared light emitting elements, a light receiving unit disposed on the two adjacent sides of the display panel, and a touch control unit including a touch coordinate calculation unit to calculate a set of coordinates of a touch point and a light emission control unit to divide optical outputs of the infrared light emitting elements into optical output during touch and optical output during non-touch and to lower the optical output during non-touch.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: July 23, 2019
    Assignee: LG DISPLAY CO., LTD
    Inventors: Young-Joon Lee, Won-Suk Lee, Hyun-Woo Jang