Patents by Inventor Young-Joon Moon
Young-Joon Moon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220157844Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.Type: ApplicationFiled: February 1, 2022Publication date: May 19, 2022Applicant: Micron Technology, Inc.Inventors: M. Jared Barclay, Merri L. Carlson, Saurabh Keshav, George Matamis, Young Joon Moon, Kunal R. Parekh, Paolo Tessariol, Vinayak Shamanna
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Patent number: 11271002Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.Type: GrantFiled: April 12, 2019Date of Patent: March 8, 2022Assignee: Micron Technology, Inc.Inventors: M. Jared Barclay, Merri L. Carlson, Saurabh Keshav, George Matamis, Young Joon Moon, Kunal R. Parekh, Paolo Tessariol, Vinayak Shamanna
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Publication number: 20200328222Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.Type: ApplicationFiled: April 12, 2019Publication date: October 15, 2020Applicant: Micron Technology, Inc.Inventors: M. Jared Barclay, Merri L. Carlson, Saurabh Keshav, George Matamis, Young Joon Moon, Kunal R. Parekh, Paolo Tessariol, Vinayak Shamanna
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Patent number: 9431264Abstract: Methods of forming integrated circuits and multiple CD SADP processes are provided that include providing a patternable structure including a first hard mask layer and a first patternable layer underlying the first hard mask layer. Mandrels are provided over the first hard mask layer. Sidewall spacers are formed adjacent sidewalls of the mandrels. The mandrels are removed, with the sidewall spacers remaining and defining gaps therebetween. The first hard mask layer is etched through the gaps to form a first patterned hard mask feature and a second patterned hard mask feature. A critical dimension of the first patterned hard mask feature is selectively modified to form a biased hard mask feature. A space is defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature. The first patternable layer is etched through exposed material in the space.Type: GrantFiled: August 30, 2013Date of Patent: August 30, 2016Assignee: GLOBALFOUNDRIES, INC.Inventors: Linus Jang, Young Joon Moon, Ryan Ryoung Han Kim
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Publication number: 20150064912Abstract: Methods of forming integrated circuits and multiple CD SADP processes are provided that include providing a patternable structure including a first hard mask layer and a first patternable layer underlying the first hard mask layer. Mandrels are provided over the first hard mask layer. Sidewall spacers are formed adjacent sidewalls of the mandrels. The mandrels are removed, with the sidewall spacers remaining and defining gaps therebetween. The first hard mask layer is etched through the gaps to form a first patterned hard mask feature and a second patterned hard mask feature. A critical dimension of the first patterned hard mask feature is selectively modified to form a biased hard mask feature. A space is defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature. The first patternable layer is etched through exposed material in the space.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Linus Jang, Young Joon Moon, Ryan Ryoung Han Kim
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Patent number: 7902609Abstract: A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.Type: GrantFiled: November 18, 2009Date of Patent: March 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Seo-woo Nam, Ki-chul Kim, Young-joon Moon, Jae-ouk Choo, Hong-jae Shin, Nae-in Lee
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Patent number: 7816137Abstract: Since the multipotent progenitor/stem cells isolated and cultured from the cord blood-derived mononuclear cells according to the method of the present invention are capable of differentiating into several types of cells including neurons, osteoblasts, myoblasts, endothelial cells, hepatocytes and dendritic cells, they can be effectively used for a cell therapy, a cell restoration technique or an organ production.Type: GrantFiled: January 31, 2005Date of Patent: October 19, 2010Assignees: Lifecord Inc.Inventors: Myoung Woo Lee, Young Jin Kim, Jeong Eun Choi, Mal Sook Yang, Young Joon Moon, Sun Kyung Kim, Hugh Chul Kim, Joon Seong Park, In Keun Jang
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Patent number: 7759185Abstract: A semiconductor device includes a first stress film covering a first gate electrode and first source/drain areas of a first transistor area and at least a portion of a third gate electrode of an interface area, a second stress film covering a second gate electrode and second source/drain areas of a second transistor area and overlapping at least a portion of the first stress film on the third gate electrode of the interface area, and an interlayer insulating film formed on the first and the second stress film.Type: GrantFiled: September 11, 2007Date of Patent: July 20, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seo-woo Nam, Young-joon Moon, Hong-jae Shin, Nae-in Lee
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Publication number: 20100065919Abstract: A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.Type: ApplicationFiled: November 18, 2009Publication date: March 18, 2010Inventors: Seo-woo Nam, Ki-chul Kim, Young-joon Moon, Jae-ouk Choo, Hong-jae Shin, Nae-in Lee
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Patent number: 7642148Abstract: A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.Type: GrantFiled: September 7, 2007Date of Patent: January 5, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seo-woo Nam, Ki-chul Kim, Young-joon Moon, Jae-ouk Choo, Hong-jae Shin, Nae-in Lee
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Patent number: 7638423Abstract: A method of forming wires of a semiconductor device including forming a first metal wire on a semiconductor substrate; forming a first insulating film on the first metal wire; etching a portion of the first insulating film to expose a surface portion of the first metal wire; forming a first barrier metal film on sidewalls of the opening and the exposed first metal wire; etching a portion of the first barrier metal film on the first metal wire to expose a surface portion of the first metal wire; performing a heat treatment process on the exposed surface portion of the first metal wire to improve surface roughness; and forming a second wire by filling the opening using a conductive material.Type: GrantFiled: February 2, 2007Date of Patent: December 29, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-eun Lee, Young-jin Wee, Andrew-tae Kim, Young-joon Moon
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Publication number: 20080272436Abstract: A semiconductor device includes a first stress film covering a first gate electrode and first source/drain areas of a first transistor area and at least a portion of a third gate electrode of an interface area, a second stress film covering a second gate electrode and second source/drain areas of a second transistor area and overlapping at least a portion of the first stress film on the third gate electrode of the interface area, and an interlayer insulating film formed on the first and the second stress film.Type: ApplicationFiled: September 11, 2007Publication date: November 6, 2008Inventors: Seo-woo Nam, Young-joon Moon, Hong-jae Shin, Nae-in Lee
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Publication number: 20080079087Abstract: A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.Type: ApplicationFiled: September 7, 2007Publication date: April 3, 2008Inventors: Seo-woo Nam, Ki-chul Kim, Young-joon Moon, Jae-ouk Choo, Hong-jae Shin, Nae-in Lee
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Patent number: 7307014Abstract: A method of forming a via contact structure using a dual damascene process is disclosed. According to one embodiment a sacrificial layer is formed on an insulating interlayer during the formation of a preliminary via hole. The sacrificial layer has the same composition as a layer filling the preliminary via hole in a subsequent trench formation process. The sacrificial layer and the layer filling the preliminary via hole are simultaneously removed after the trench formation process is carried out. According to another embodiment, a thin capping oxide layer is formed on an insulating interlayer during the formation of a preliminary via hole. The thin capping oxide layer is removed together with a sacrificial layer after a trench formation process is carried out.Type: GrantFiled: April 6, 2005Date of Patent: December 11, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hak Kim, Kyoung-Woo Lee, Hong-Jae Shin, Young-Joon Moon, Seo-Woo Nam
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Publication number: 20070224855Abstract: A method of forming wires of a semiconductor device including forming a first metal wire on a semiconductor substrate; forming a first insulating film on the first metal wire; etching a portion of the first insulating film to expose a surface portion of the first metal wire; forming a first barrier metal film on sidewalls of the opening and the exposed first metal wire; etching a portion of the first barrier metal film on the first metal wire to expose a surface portion of the first metal wire; performing a heat treatment process on the exposed surface portion of the first metal wire to improve surface roughness; and forming a second wire by filling the opening using a conductive material.Type: ApplicationFiled: February 2, 2007Publication date: September 27, 2007Inventors: Jung-eun Lee, Young-jin Wee, Andrew-tae Kim, Young-joon Moon
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Publication number: 20060183280Abstract: There are provided metal-insulator-metal (MIM) capacitors and methods of forming the same. The capacitors and the formation methods thereof provide a way of simplifying semiconductor fabrication processes, using component elements of the capacitor and insulating layers around the capacitor. To this end, lower and upper electrodes are sequentially stacked on a semiconductor substrate. A dielectric layer pattern is interposed between the upper and lower electrodes. An etch stop layer pattern and an etch buffer layer are disposed on the upper electrode and under the lower electrode, respectively. The upper and lower electrodes are disposed to expose the dielectric layer pattern and the etch buffer layer.Type: ApplicationFiled: February 13, 2006Publication date: August 17, 2006Inventors: Sang-Jin Lee, Young-Joon Moon, Seung-Koo Lee, Kyung-Tae Lee
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Patent number: 7064059Abstract: There is provided a method of forming a dual damascene metal interconnection by employing a sacrificial metal oxide layer. The method includes preparing a semiconductor substrate. An interlayer insulating layer is formed on the semiconductor substrate, and a preliminary via hole is formed by patterning the interlayer insulating layer. A sacrificial via protecting layer is formed on the semiconductor substrate having the preliminary via hole to fill the preliminary via hole, and cover an upper surface of the interlayer insulating layer. A sacrificial metal oxide layer is formed on the sacrificial via protecting layer, the sacrificial metal oxide layer is patterned to form a sacrificial metal oxide pattern having an opening crossing over the preliminary via hole, and exposing the sacrificial via protecting layer.Type: GrantFiled: September 13, 2004Date of Patent: June 20, 2006Assignee: Samsung Electronics, Co., LtdInventors: Jae-Hak Kim, Young-Joon Moon, Kyoung-Woo Lee, Jeong-Wook Hwang
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Publication number: 20060003574Abstract: A method of forming a via contact structure using a dual damascene process is disclosed. According to one embodiment a sacrificial layer is formed on an insulating interlayer during the formation of a preliminary via hole. The sacrificial layer has the same composition as a layer filling the preliminary via hole in a subsequent trench formation process. The sacrificial layer and the layer filling the preliminary via hole are simultaneously removed after the trench formation process is carried out. According to another embodiment, a thin capping oxide layer is formed on an insulating interlayer during the formation of a preliminary via hole. The thin capping oxide layer is removed together with a sacrificial layer after a trench formation process is carried out.Type: ApplicationFiled: April 6, 2005Publication date: January 5, 2006Inventors: Jae-Hak Kim, Kyoung-Woo Lee, Hong-Jae Shin, Young-Joon Moon, Seo-Woo Nam
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Publication number: 20050124149Abstract: There is provided a method of forming a dual damascene metal interconnection by employing a sacrificial metal oxide layer. The method includes preparing a semiconductor substrate. An interlayer insulating layer is formed on the semiconductor substrate, and a preliminary via hole is formed by patterning the interlayer insulating layer. A sacrificial via protecting layer is formed on the semiconductor substrate having the preliminary via hole to fill the preliminary via hole, and cover an upper surface of the interlayer insulating layer. A sacrificial metal oxide layer is formed on the sacrificial via protecting layer, the sacrificial metal oxide layer is patterned to form a sacrificial metal oxide pattern having an opening crossing over the preliminary via hole, and exposing the sacrificial via protecting layer.Type: ApplicationFiled: September 13, 2004Publication date: June 9, 2005Inventors: Jae-Hak Kim, Young-Joon Moon, Kyoung-Woo Lee, Jeong-Wook Hwang