Abstract: Provided is an image recognition apparatus that identifies a person through a face of the person recognized from a photographed image, an image recognition method thereof and a face image generation method thereof. The method for recognizing a face image includes generating candidate images including at least one morphable image which is generated using an object image, extracting first features from the generated candidate images, extracting second feature from a reference image, and generating at least one score corresponding to each of the at least one morphable image by comparing the first features with the second feature, and performing matching to calculate a final score from the generated at least one score.

Abstract: Provided is a method and apparatus for inferring a facial composite, whereby user's designation regarding at least one point of a facial image is received, facial feature information are extracted based on the received user's designation, a facial type that coincides with the extracted facial feature information is searched from a facial composite database to generate a face shape model based on the searched facial type and an initial facial composite model having a facial type similar to a face of the facial image from a low-resolution facial image through which face recognition or identification cannot be accurately performed is provided, so that the face shape model contributes to criminal arrest and a low-resolution facial image captured by a surveillance camera can be more efficiently used.

Abstract: A driving integrated circuit and methods thereof are provided. The driving IC includes a memory for driving a display panel and having a memory structure including at least one cell block, a scan register receiving data read from the memory, a source driver receiving data output from the scan register and outputting the received latched data to the panel and a switching unit establishing a connection between an activated cell block and the scan register in response to an activation of the activated cell block. One method includes performing a read operation to read data from a memory, the read operation including sensing and amplifying data stored within a memory cell, turning on a switch to increase a bit line voltage above a voltage threshold and latching the amplified data received through a line connected to the switch and transmitting the read data to the panel of the display device.

Abstract: In a semiconductor device and a method of manufacturing the same, a substrate is defined into active and non-active regions by a device isolation layer and a recessed portion is formed on the active region. A gate electrode includes a gate insulation layer on an inner sidewall and a bottom of the recessed portion, a lower electrode on the gate insulation layer and an inner spacer on the lower electrode in the recessed portion, and an upper electrode that is positioned on the inner spacer and connected to the lower electrode. Source and drain impurity regions are formed at surface portions of the active region of the substrate adjacent to the upper electrode. Accordingly, the source and drain impurity regions are electrically insulated by the inner spacer in the recessed portion of the substrate like a bridge, to thereby sufficiently prevent gate-induced drain leakage (GIDL) at the gate electrode.

Abstract: In a semiconductor device and a method of manufacturing the same, a substrate is defined into active and non-active regions by a device isolation layer and a recessed portion is formed on the active region. A gate electrode includes a gate insulation layer on an inner sidewall and a bottom of the recessed portion, a lower electrode on the gate insulation layer and an inner spacer on the lower electrode in the recessed portion, and an upper electrode that is positioned on the inner spacer and connected to the lower electrode. Source and drain impurity regions are formed at surface portions of the active region of the substrate adjacent to the upper electrode. Accordingly, the source and drain impurity regions are electrically insulated by the inner spacer in the recessed portion of the substrate like a bridge, to thereby sufficiently prevent gate-induced drain leakage (GIDL) at the gate electrode.

Abstract: A memory layout where the pre-charger circuits are connected between different pairs of bit lines than are the sense amplifiers: The two bits lines in each bit line pair are connected to different pre-charge circuits and thus they can be charged to different pre-charge voltages. That is, the bit line and bit line bar sense lines in each bit line pair are connected to different pre-charge circuits. With this configuration it is possible to perform a sense stress test by activating all of the address lines at the same time and to charge to bit line and the bit bar line in each pair of sense lines to different voltages. With this configuration it is possible to reduce the number of test pads required.

Abstract: A driving integrated circuit (IC) and methods thereof are provided. The example driving IC may include a memory storing data for driving a panel of a display device and having a memory structure including at least one cell block, a scan register receiving data read from the memory and latching the received read data, a source driver receiving data output from the scan register and outputting the received latched data to the panel and a switching unit selectively establishing a connection between an activated cell block and the scan register in response to an activation of the activated cell block, the activated cell block included among the at least one cell block of the memory.

Abstract: A semiconductor integrated circuit device and a method of fabricating the same are provided. An embodiment of the semiconductor integrated circuit device includes a substrate having a cell region and a peripheral circuit region. A recess channel transistor may be formed in the cell region and include a source/drain region, a recess channel formed between the source/drain region, a gate insulation layer formed in the recess channel, and a gate formed on the gate insulation layer in a self-aligned manner. A planar channel transistor may further be formed in the peripheral circuit region and include a source/drain region, a planar channel formed between the source/drain region, a gate insulation layer formed in the planar channel, and a gate formed on the gate insulation layer in a self-aligned manner.

Abstract: A memory layout where the pre-charger circuits are connected between different pairs of bit lines than are the sense amplifiers: The two bits lines in each bit line pair are connected to different pre-charge circuits and thus they can be charged to different pre-charge voltages. That is, the bit line and bit line bar sense lines in each bit line pair are connected to different pre-charge circuits. With this configuration it is possible to perform a sense stress test by activating all of the address lines at the same time and to charge to bit line and the bit bar line in each pair of sense lines to different voltages. With this configuration it is possible to reduce the number of test pads required.

Abstract: A method of isolating epithelial cells from a human skin tissue or internal organ tissue using trypsin and ethylene-diamine tetraacetic acid (EDTA) simultaneously with the application of magnetic stirring, a method of preconditioning isolated biological cells by the application of physical stimulus, i.e., strain, are provided. Epithelial cells can be isolated by the method with increased yield, colony forming efficiency (CFE), and colony size. Also, the increased percentage of stem cells in isolated cells is advantageous in therapeutic tissue implantation by autologous or allogeneic transplantation. In skin cells preconditioned by the application of strain, cell division is facilitated, and the secretion of extracellular matrix components and growth factors and the activity of matrix metalloproteinases (MMPs) are improved.